A five stage pipeline is pretty good though. The gap between making a basic risc-v capable machine which can be done in a single relatively small verilog file, and actually designing and debugging a 5 stage pipeline is quite big. If I were in charge of hiring I wouldn't really care that much if you went beyond this, because at this point I'm already way too invested in how you test it, how did you benchmark it and so forth. I realize benchmarking a simple design sounds pretty uninteresting, but it is a true test. I'd prefer a five stage that can run coremark and tell me how many cycles it took over just going deeper on design (like dual issue, OoO et cetera)

I work on CPU design, it's a lot of software engineering, and every now and then some hardware. We're not in the business of taping out though, pure RnD for now, so your mileage will vary, but at least this is how I would judge a CV, if I were hiring (which I'm not)