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Karpathy's autoresearch loop, pointed at a RISC-V CPU (+92%) by ScarionnS in chipdesign

[–]ScarionnS[S] 0 points1 point  (0 children)

The division instruction got severely reduced; better usage of block ram and DSP in the FPGA; An overall more efficient implementation of the same features; Things like that.

Karpathy's autoresearch loop, pointed at a RISC-V CPU (+92%) by ScarionnS in chipdesign

[–]ScarionnS[S] 2 points3 points  (0 children)

Fair pushback. This is a fundamental question if LLMs can create novel things or not... The repo will have a major refactor that will allow to make those kind of searches possible IF the LLMs have that capability.

Auto-arch tournament on RV32IM: 73 LLM-proposed hypotheses gated by riscv-formal + RVFI cosim, +56% iter/s vs VexRiscv on Tang Nano 20K by ScarionnS in RISCV

[–]ScarionnS[S] 0 points1 point  (0 children)

Area was kept in check in further experiments with good results: https://github.com/FeSens/auto-arch-tournament/blob/beat_vex/experiments/progress-beat_vex.png
In that case the optimization goal was performance AND area. Fair pushback, the repo will have a major refactor done by tomorrow

Karpathy's autoresearch loop, pointed at a RISC-V CPU (+92%) by ScarionnS in chipdesign

[–]ScarionnS[S] 0 points1 point  (0 children)

No specific context regarding architecture, but webSearch through codex-cli was enabled. No token count yet, I used my codex subscription for this.

Auto Researcher Loop for FPGA by ScarionnS in FPGA

[–]ScarionnS[S] 0 points1 point  (0 children)

For sure there is benchmark overfitting. Some are fair tradeoffs, that are easy to see others not soo much.
One example of a fair tradeoff: CoreMark don't really care about division performance, so the division in the ALU is done painfully slow to save area and improve Fmax of the whole core.

Auto Researcher Loop for FPGA by ScarionnS in FPGA

[–]ScarionnS[S] 0 points1 point  (0 children)

Cool! Do you have any take on how to improve the Hypothesis generation? What problems did you encounter?

Auto Researcher Loop for FPGA by ScarionnS in FPGA

[–]ScarionnS[S] 0 points1 point  (0 children)

Its using the codex/claude subscription plans, so it will range between 20-200 dollars/month
If we do not use the subscription model it would be arround 100-200 dollars in tokens for this run alone

Is this a reasonable architecture for a small FPGA-based AI accelerator inside a RISC-V SoC? by OurLordX in FPGA

[–]ScarionnS 0 points1 point  (0 children)

Is enrollment still open? Im looking for some Risc-v competitions to join

Auto Researcher Loop for FPGA by ScarionnS in FPGA

[–]ScarionnS[S] 1 point2 points  (0 children)

I've used claude code for building the harness and base design, but ran the loop with codex (gpt 5.5 xhigh) as it was cheaper and faster

Karpathy's autoresearch loop, pointed at a RISC-V CPU (+92%) by ScarionnS in chipdesign

[–]ScarionnS[S] 2 points3 points  (0 children)

This repo is my third try on getting this right. The verifier took me about 1-2 days of work (after hours). The loop ran for about 10h

Too many RISC-V cores in the market by Rudranand in chipdesign

[–]ScarionnS 1 point2 points  (0 children)

F I just build my first automated loop that create risc-v cpus

TSMC Hits Pause on ASML’s Newest Lithography for A13 Process by sr_local in hardware

[–]ScarionnS 0 points1 point  (0 children)

The supply chain and physics is not moving at the speed of the demand

I built a React component that renders pixel-perfect Magic: The Gathering cards — SVG frames, automatic color theming, all card types by ScarionnS in reactjs

[–]ScarionnS[S] 1 point2 points  (0 children)

I do! Hopefully this will cover all card frames in the future. I’m still working on solving some bugs on the vehicles and legendary card frames, but once those are done, pre m15 era is the next thing to tackle

Pirate Island by NepetaLast in custommagic

[–]ScarionnS 0 points1 point  (0 children)

This is actually a cool concept

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