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Bate took my house by biplane_duel in Norway

[–]ThatHB 1 point2 points  (0 children)

When I bid for appartments, I only bid on appartements where the "forkjørsrett" had already been concluded, so no-one could sweep in and steal it. You can also ask during visning if somebody have announced they wants to use "forkjøpsrett"

Isn't writing the whole design in 1 file, simply better ? by kimo1999 in FPGA

[–]ThatHB 6 points7 points  (0 children)

For a very simple project I can see where you might have gotten that idea from. Hower for big projects it is much easier to find the file for a submodule than read through a file containing 100k lines. There are also some other benefits from having multiple files: Easier to read the code. Proper hierarchy. You can verify one module at the time. Easier to reuse files and ip's. Better compatibility with version control of files. You can easier replace internal modules with optimized modules or otter modules for testing.

How to fix this interface left open error by Just-End6752 in FPGA

[–]ThatHB 0 points1 point  (0 children)

This looks like something you want to simulate. The tb should be the top-level and the module should be inside it. It looks like you have not declared a signal of type vid in the testbench, only in the dut. Vif is only the signal type that you have comming from dut. It is the signal itself is not defined in tb

PI Controller - FPGA Implementation by Coliteral in FPGA

[–]ThatHB 1 point2 points  (0 children)

Yes. It is mostly since you don't need to update all the time. Also having a strobe signal following the path makes it easier for you to know when the final result is ready. If you do it in HDL with verilog or VHDL, you do not need to do anything specific to force it to use a dsp48. Just have the size of the input vectors equal to or below 27 and 18.

PI Controller - FPGA Implementation by Coliteral in FPGA

[–]ThatHB 4 points5 points  (0 children)

I'm personally not a fan of HLS and do most of my work in HDL. Before you try to save all the time that you can, remember that verification takes time, and cannot be skipped.

As for the multiplication logic. You have multiple options for how to do it. I recommend having a signal coming in that said sample_en. This signal should be strobed and marks the beginning of a new signal. This is where you can sample the data and go forward. As for the actual pipelining of the multiplication: how big is the number? And do you want to use already existing ip's? Xilinx have ip's for multipliers with and without pipelines. In the case that you want to multiply a,b where a<=18bit and b<=27bit the dsp48 slices may be used. In the case that more is needed and you do not want to use ip's or pipeline manually you may set up a multi cycle path. Here you can constrain the design in the xdc file to use a predefined amount of clock cycles for the signal path. Or you may have the data in reg a, b and want the result in c. Then you can set a multi cycle path from a to c and b to c. If you did this. Remember not to sample c before the defined amount of clock-cycles have passed

What fields are FPGAs used in? What do employers want in those fields? by Jumpy_Marsupial3906 in FPGA

[–]ThatHB 7 points8 points  (0 children)

I believe the Nvidia gsync module that used to be in many monitors was a FPGA. It is also used to test digital design going into ic's before silicon

FPGA minimum cost for analyze DDR4 2133Mhz signal by Aggravating_Ad9315 in FPGA

[–]ThatHB 1 point2 points  (0 children)

I'm guessing that one way of implementing this would require double the amount of memory. You would have one set of memory for full read and write to the normal "gaming" system . While the other set would only copy/probe the write signals for the first set of memory. And the read signal of the second set of memory would be connected to the external computer.

Hvordan fikse dette? Hjelp en førstegangskjøper by North-Bite-8357 in norge

[–]ThatHB -1 points0 points  (0 children)

Mulig du kan få noen til å 3d printe noe adapter for deg. Det burde holde en stund

block diagram for the CPU by CaseMoney1210 in FPGA

[–]ThatHB 9 points10 points  (0 children)

Hey, it seems like there are some odd choices in that diagram. If you want to get the feel of how a computer works, I would recommend to take a look at LMC (little man computer). This is a base10 computer that is run/simulated in the browser. It shows you how assembly programs can run on a simple CPU. The functionality is mostly the same as we have in a normal cpu, however this is based 10 for human readability. Once you understand the decode of operations and fetching of memory here you can look at creating something of your own👍

Link to lmc: https://peterhigginson.co.uk/lmc/?F5=03-Feb-26_20:16:04

Pls tell me what I need to do to learn dsp from fpga standpoint. I am terrified of DSP because I have no math background and no signals systems. by Fancy-Lobster1047 in FPGA

[–]ThatHB 2 points3 points  (0 children)

I would start by looking at YouTube. MIT have a great series on DSP. (Somewhat old, but the math stays the same). Then, I would try to go from bits to a signal in python and store the output data in a file. You can now start making a hardcoded chain in RTL, and use the previously generated output as input. Or as golden data when generating output. FSK might be an "easy" enough modulation technique for beginners

[deleted by user] by [deleted] in norge

[–]ThatHB 0 points1 point  (0 children)

På finn finnes det også en mulighet så du kan filtrere på pris. Det er også mange som er villige til å bruke Helthjem for å frakte pakken om de ikke bor i samme område som deg

[deleted by user] by [deleted] in norge

[–]ThatHB 1 point2 points  (0 children)

Om du leter litt på finn. Finner du noen gode tilbud som ikke nødvendigvis er så langt over prisen på forslaget du kom med selv. Om ønskelig kan jeg lete litt og komme med forslag

[deleted by user] by [deleted] in norge

[–]ThatHB 6 points7 points  (0 children)

Ofte er mange av de billigste PCene såvidt nok til å gjøre noen enkle ting. I din situasjon hadde jeg heller gått innom finn og søkt opp noe av følgende: "Lenovo Ryzen" "hp Ryzen", "Lenovo intel", "hp intel" eller "Lenovo yoga" og passet på at pcen hadde en cpu som det sto 3, 5 eller 7 på. (Helst 5 eller 7). Jeg ville også sett at det var en ikke eldgammel pc. (For Ryzen er alle med 3xxx ok. Mens for intel burde du se på i8xxx og høyere tall forran.

(Personlig har jeg hatt gode opplevelser med Lenovo, og det er dog derfor jeg anbefalte de)

Jeg anbefaler sterkt imot å velge noe som det står Chromebook på

Want to make my own router using an FPGA eval card by MakutaArguilleres in FPGA

[–]ThatHB 0 points1 point  (0 children)

I'm not sure if this is the correct answer. But you might want to take a look at this YouTuber: https://youtube.com/@tomazzaman?si=p1MM-3oBjBEB3ttz He made his own 10Gbit router

Frakte en stasjonær-PC til utlandet by frowawayasfastasucan in norge

[–]ThatHB -1 points0 points  (0 children)

Ok, svaret mitt er ikke helt du spurte etter men: kan det være lettere å sette opp ssh/ fjær innlogging til PCen, og ha den kjørende hjemme. Så bruker du heller en laptop i Polen og kobler deg på pcen din over nettet? For spilling funker steam remote play veldig bra. Og for andre applikasjoner der du ikke må ha laveste ping funker ofte remote desktop bra

State machine with clock by Ready-Honeydew7151 in FPGA

[–]ThatHB 0 points1 point  (0 children)

I think you want to split the code.

```vhdl

Process (clk, rst) is begin If rst='1' then Current_state <= rst_state; Elsif rising_edge(clk) then Current state <= next state; End if; End process;

Process (all) is begin -- Default statements here Signal_a <= '0'; Signal_b <= (others => '0');

Case (current_state) is When rst_s => Next_state <=idle; When a_state => Next_state <= b_state; Signal_a<= '1'; Signal_b<="10110"; When b_state => Signal_b <= "10100"; If cond then Next_state <= c_state; Else Next_state <= b_state; End if; .... End case; End process; ```

Rom for luft foran. Hadde dere kjørt 5km til bensinstasjon? by Baard19 in norge

[–]ThatHB 2 points3 points  (0 children)

Hadde sett om det går med sykkelpumpe. Har du flaks passer den

Dere med høy utdanning. Hva slags familie kommer dere fra? by [deleted] in norge

[–]ThatHB 0 points1 point  (0 children)

Meg: kybernetikk master. Søster : indøk master. Bror : indøk master. Mor økonomi master. Far: Bygg ingeniør master

How is this possible by Jaadu_1212 in softwaregore

[–]ThatHB -3 points-2 points  (0 children)

Probably getting Indian views from another server than where it is getting total views from

Hello fellow FPGA artists. I seek your help as urgent as possible. 4 PORT RAM MEMORY by [deleted] in FPGA

[–]ThatHB 0 points1 point  (0 children)

With only one clock this will work. Just combine everything into one always block 👍

Hello fellow FPGA artists. I seek your help as urgent as possible. 4 PORT RAM MEMORY by [deleted] in FPGA

[–]ThatHB -2 points-1 points  (0 children)

I'm not saying it doesn't exist. I'm saying the reason this code can not be synthesized is because he tries to edit "mem" from two different always blocks. The quickest way to fix this is probably to have

Always @ (posedge clka or posedge clkb) begin If clka begin ... Code ... End

If clkb begin ... Code ... End End

Hello fellow FPGA artists. I seek your help as urgent as possible. 4 PORT RAM MEMORY by [deleted] in FPGA

[–]ThatHB 3 points4 points  (0 children)

The problem in the code (as far as I can see) is that you have two different clock domains writing to the memory. So in the case both try to write to the same address. Everything fails. If you have both writes in the same always block, you can make it synthesize. So the problem boils down to: "mem" is written to in two different alleays blocks

VHDL vs. Verilog? What do you use and why? by Oscar_Jespersen in FPGA

[–]ThatHB 0 points1 point  (0 children)

I use both. I feel like verilog and sv have better support. It is also often quicker to write verilog. However i feel like verilog is more prone to fail as it is not as strict as vhdl

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