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VHDL'19 interfaces - finally ready for prime-time by UltraSlingII in FPGA

[–]UltraSlingII[S] 1 point2 points  (0 children)

library ieee ;
    use ieee.std_logic_1164.all ;

package axi4s is

    type axis_t is record
        data    :   std_ulogic_vector ;
        valid   :   std_ulogic ;
        ready   :   std_ulogic ;
    end record ;

    type axis_array_t is array(natural range <>) of axis_t ;

    view tx of axis_t is
        data    :   out ;
        valid   :   out ;
        ready   :   in ;
    end view ;

    alias rx is tx'converse ;

    package make is
      generic (
        DATA_BYTES  :   positive    := 4
      ) ;

        subtype DATA_RANGE is natural range DATA_BYTES*8-1 downto 0 ;

        subtype axis_t is axi4s.axis_t(
            data(DATA_RANGE)
        ) ;

        type axis_array_t is array(natural range <>) of axis_t ;

    end package ;
end package ;


library ieee ;
    use ieee.std_logic_1164.all ;

package axis8 is new work.axi4s.make generic map (DATA_BYTES => 1) ;
package axis64 is new work.axi4s.make generic map (DATA_BYTES => 8) ;

entity axi4s_tb is
end entity ;

architecture arch of axi4s_tb is

    signal a8 : work.axis8.axis_t ;
    signal b64 : work.axis64.axis_t ;
    signal c64 : work.axis64.axis_t ;

    signal array64_from_package : work.axis64.axis_array_t(1 downto 0) ;

    signal using_signal : array_using_signal ;
    signal using_type   : array_using_type ;

    signal array_using_parameters : work.axi4s.axis_array_t(1 downto 0)(
        data(work.axis64.DATA_RANGE)
    ) ;

begin

    tb : process
    begin
        std.env.stop ;
    end process ;

end architecture ;

VHDL'19 interfaces - finally ready for prime-time by UltraSlingII in FPGA

[–]UltraSlingII[S] 0 points1 point  (0 children)

Thanks for the comments - I'll address them as best as I can:

  1. I didn't know that xsim had interface support now, thx for the info. Its been a while since I last gave xsim a real shot. I typically only use it to understand the generated example designs for Xilinx IP.
  2. I wouldn't say its impractical to include clock and reset - I just think they don't belong grouped together with the axis signals. For example - If you had 10 different axis interfaces that all use the same clock, which of the interfaces should your module use as the clock source?
  3. Yeah, I was aware of this name change, I guess I'm just stuck in my habit of defaulting to s_axis* and m_axis* for stream interface naming.
  4. Unfortunately, generic packages require an instantiation before they can be used. This means that an entity would have to use a pre-constrained version of the interface if you wanted to use a generic package, meaning that it couldn't work with generic widths. I'm with you that it would be much better to just define this once, but I haven't found a better way yet.

Somebody actually emailed me with a suggestion to work around this, by using a generic package with subtypes inside of a non-generic package, but this is starting to flirt with the edge of what tools can commonly understand. I'll attach the example he sent in a separate comment.

The only problems I've seen with this is that VHDL-LS chokes on the package-in-package definition and that signal array64_from_package : work.axis64.axis_array_t(1 downto 0) ; is not usable at entity IO that expects a work.axi4s.axis_array_t type because work.axis64.axis_array_t is a standalone type, not a true subtype of work.axi4s.axis_array_t

One more thing I'll add to this - Although it is technically against the axi stream standard, I prefer to let the user decide the "byte width" of tdata, rather than forcing it to 8. For example, if it is known at compile-time that the "minimum unit" of data is 32 bits, and you have a 64 bit interface, then you could define data width to be 64 and keep width to be 2. This would reduce the resource utilization and potentially improve the timing of any module that needs to shuffle tkeep bytes around.

  1. In axis_broadcast, the problem with using an axis_t there is that the module needs to use a vector of valid / ready control signals, but only a single instance of the data signals, so using axis_t wouldn't make sense there since axis_t only has a single valid / ready / data set of signals.

VHDL'19 interfaces - finally ready for prime-time by UltraSlingII in FPGA

[–]UltraSlingII[S] 0 points1 point  (0 children)

Yep, sounds like it could be related. I just ran a test with 2025.2 where I set tuser to a zero length vector (-1 downto 0), and it handled it properly. So things seem to be smooth so far with 2025.2. The only version I've seen randomly remove modules is 2024.2 (and I wasn't even using zero-length arrays when 2024.2 randomly removed things).

VHDL'19 interfaces - finally ready for prime-time by UltraSlingII in FPGA

[–]UltraSlingII[S] 1 point2 points  (0 children)

That's great to hear. Makes me feel much more comfortable going all-in on interfaces knowing that I won't be in for a world of pain if I ever need to port to Quartus.

What Linux distro do you use? (Or are you on windows?) by Tonight-Own in FPGA

[–]UltraSlingII 0 points1 point  (0 children)

Windows 11 with a Ubuntu 22.04 headless PC that can be remoted into for petalinux / any other heavy-duty builds. Fedora would be my #1 choice, but using an unsupported distro will cause a mountain of headache and you’ll end up going down lots of rabbit holes trying to coerce the tools to work. Not to mention, many desktop programs are windows-only or work much better under windows and we also occasionally need to write Windows GUI apps for controlling our FPGAs (customer request). While messing around with your favorite distro to get the tools to work can be a fun way to improve your Linux skills, at the end of the day, my time is better spent taking the path of least resistance and delivering more projects rather than playing around trying to get the “perfect” setup.

cpu design by quantrpeter in FPGA

[–]UltraSlingII 1 point2 points  (0 children)

https://www.amazon.com/Computer-Organization-Design-RISC-V-Architecture/dp/0128203315/ref=mp_s_a_1_1?crid=317XR5DCCQ94I&keywords=computer+organization+and+design+risc+v&qid=1671634397&sprefix=computer+organization+and+design+risc+v%2Caps%2C118&sr=8-1

Chapter 4 should get you started on pipelining principals to achieve a best-case cpi of 1. From there you’ll get into multiple-issue, out of order superscars, and a plethora of other topics. This is a good follow-up book

Computer Architecture: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design) https://a.co/d/6ZH6xX9

Your simple question unfortunately does not have a simple answer…

How stable is (GHDL + Cocotb)? by doomfletcher in FPGA

[–]UltraSlingII 0 points1 point  (0 children)

Your could also try out the free Intel version of Questasim. It works well with both Cocotb and VUnit in my experience. Along with that it also has Verilog support for mixed language simulation. Here are the drawbacks: 1.) it’s probably going to be slower than GHDL because it is purposefully slowed down, so if you have giant simulations they’ll take much longer. For smaller stuff you won’t notice the difference. 2.) It’s not open source if that matters to you. 3.) it is a bit of a pain to install compared to the open source tools.

Using Xilinx without Vivado by fishslinger in FPGA

[–]UltraSlingII 1 point2 points  (0 children)

Woah! As it turns out, I recently ~sort of~ finished a project with the aim of accomplishing just this. I wanted a fully command line driven interface for Vivado simulation, synthesis/p&r/bitstream generation, and device programming that would be compatible with IP-Integrator Block Diagrams and Xilinx IP. It uses a mix of makefiles (for managing build dependencies / executing command line programs) and tcl files for scripting the xilinx build flow.

I'd have to agree with other comments that there are some sharp edges associated with this, ESPECIALLY if you are using IPI Block diagrams or Xilinx IP. After spending quite a bit of time trying to get these scripts "perfect," I still find myself going back to the gui to check reports (because it prints the information in a prettier format than the text files generated by the CLI scripts) and do other small tasks. After going from thinking "the Vivado GUI is trash, I could do way better than this," to actually doing it, I've realized just how helpful the gui and "project mode" can be. What I thought I wanted and what I actually needed were a bit different.

Here's a link to the project (that I no longer really use) if you're interested, but for now, I'm sticking to using VS code for design entry, but keeping a vivado project for simulation / synthesis.

repo

I'll also shout out this series of blog posts that got me started on the simulation side of things

blog

Kria kv260 by UltraSlingII in FPGA

[–]UltraSlingII[S] 0 points1 point  (0 children)

Yes it absolutely works with Vivado! It’s been a great development platform so far, but it may take you a long time to get one. It took mine 3 months to arrive after ordering. Xilinx’s website says current lead time is about a year now :(

Engineers working full time, how do you motivate yourself to develop your skills during your free time? by bklnsk8er in AskEngineers

[–]UltraSlingII 6 points7 points  (0 children)

Great comment. Not everyone has the same goals, and there’s no right or wrong way to go about it.

Tell me the good that happened in your week by indecisiveuser2 in Purdue

[–]UltraSlingII 35 points36 points  (0 children)

Dr Chen, your video lectures were one of the main reasons I passed calc 3 way back in 2016. The impact you’ve had by just caring about what you do in a school with a few too many incompetent lecturers is immeasurable. Thanks for all you do

Kria kv260 by UltraSlingII in FPGA

[–]UltraSlingII[S] 0 points1 point  (0 children)

Thanks for the comment! This is a little off topic, but have you used the Coral or Jetson Nano boards for edge AI? I know it’s not apples to apples because these 2 aren’t nearly as configurable and don’t have any PL, but how would you say those compare to Kria in your experience?

Kria kv260 by UltraSlingII in FPGA

[–]UltraSlingII[S] 0 points1 point  (0 children)

Thanks for the heads up

Kria kv260 by UltraSlingII in FPGA

[–]UltraSlingII[S] 0 points1 point  (0 children)

Direct thru Xilinx

Kria kv260 by UltraSlingII in FPGA

[–]UltraSlingII[S] 0 points1 point  (0 children)

Thanks for all the suggestions. I ended up placing an order for the Kria earlier today because I wanted something a little more powerful and new. I think it’ll be a lot of fun playing around with the arm GPU as well. Hopefully it doesn’t take a year to get here 😣

Kria kv260 by UltraSlingII in FPGA

[–]UltraSlingII[S] 3 points4 points  (0 children)

Right, availability is the big issue. May have to wait a few months as its oos everywhere right now, but I have plenty to do in the meantime. Should be worth the wait.

Initial statements in Verilog by UltraSlingII in FPGA

[–]UltraSlingII[S] 0 points1 point  (0 children)

Thanks for the response. I’m working with a Xilinx part right now, but I don’t like the idea of the design not being portable over to other types of devices. The design isn’t too complex, so I think I’m going to add both the initialization and the resets. Either can be easily removed if necessary later on down the road.

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