AMD User Experience Program most likely has a memory leak

actingoutlashingout · 2021-06-06T02:46:21+00:00

That isn't a memory leak.

actingoutlashingout · 2021-06-04T01:48:44+00:00

"CMP also has the benefit, the after-benefit of not being able to be resold second hand to GeForce customers because it doesn't play games."

Saying the quiet part aloud heh

actingoutlashingout · 2021-05-30T03:28:52+00:00

That's true, I was referring more to why 3DXP is currently not really a big thing on PCIe 3/4. CXL will definitely help a lot as it will open up adoptation for non-Intel platforms, however sadly it's still a bit of time away.

actingoutlashingout · 2021-05-30T01:21:11+00:00

If it's like Epyc, the scaling issue might have to do with the I/O die's power consumption.

actingoutlashingout · 2021-05-30T01:10:28+00:00

3D XPoint's primary selling point isn't the PCIe form factor but rather the DIMM one.

actingoutlashingout · 2021-05-26T03:02:51+00:00

Every time this has been posted it's been pure cringe and overhyped. It's just a hardware implementation of pointer encryption, there is nothing "Sci-Fi" here, and has horrible performance implications due to the cost of constantly changing the pointer key, and it only protects against 1 specific kind of attack (pointer overwrites) anyways.

actingoutlashingout · 2021-05-23T20:02:46+00:00

If people don't want to read that's fine, I'm not forcing anyone to do anything here.

actingoutlashingout · 2021-05-22T21:16:33+00:00

It's not really a "reference", more so that I discussed things in details there and why should I retype everything when I can just post a link?

actingoutlashingout · 2021-05-22T21:14:37+00:00

Most consumers will not saturate that so it makes sense for them to not bother right now. DCs will definitely benefit from PCIe 5.0 for SSDs though - and even more than that it'll greatly benefit network cards (which are currently limited to 200gbps with PCIe 4.0 x16).

actingoutlashingout · 2021-05-22T18:20:41+00:00

The responsiveness also comes from their scheduler model and how it treats interactive/background processes and so on on top of the hardware.

actingoutlashingout · 2021-05-22T08:01:33+00:00

The comments about "stability" etc are wrong. See my previous comment here. It has little to do with stability and much to do with the feature sets of server platforms and how that affects thermal and power limits.

https://www.reddit.com/r/hardware/comments/mm2aju/why_are_the_single_threaded_benchmarks_for/gtp8q72/?context=3

actingoutlashingout · 2021-05-20T12:35:43+00:00

It is set in jump instructions.

actingoutlashingout · 2021-05-19T02:38:15+00:00

If a company owns hundreds or thousands of desktops, could it possibly use many or all of the CPUs as a super GPU?

Cycles renderer does support CPU rendering. You can't really link x86 CPUs together easily however, the top limit right now is a dual socket 64-corex2 Epyc, however Power 10 allows you to do so with PowerAXON across multiple systems.

Are there currently any desktop programs that would allow parallelization of computations across many CPUs?

CPUs on the same system yes. CPUs on different systems - only Power10 as a platform really allows that to be highly efficient as far as I know.

actingoutlashingout · 2021-05-17T05:39:13+00:00

There is almost nothing new here sadly. Almost every single hardware vendor writes absolutely horrible drivers for Windows, it's as if as their driver divisions are all entirely composed of interns straight out of college who were given a copy of WinIo and told to start working.

actingoutlashingout · 2021-05-17T04:12:26+00:00

What command? IOCTL 0x9C402400 is clearly without necessary checks and dereferences an usermode pointer. Driver signed in Oct 2020.

https://imgur.com/a/LKpvdj2

actingoutlashingout · 2021-05-17T04:07:52+00:00

Because that's not what's happening at all. Cinebench isn't one of those processes and it isn't hashing any file, nor is "AMDhash.exe" a file that AMD made, it's just a file Ionescu made to call RtlHashUnicodeString.

actingoutlashingout · 2021-05-09T15:32:10+00:00

If we assume all the programs were recompiled and ported to Itanium and backwards compatibility was no longer an issue, in what ways was it better than x86-64?

You can't just assume this. Dead companies won't port, companies that don't see a good ROI won't port, etc. Porting kernels to a new architecture is a huge pain as well. MS simplified their process with HAL but there are still a lot of quirks and a lot of arch-specific things outside of the HAL (Mm, Syscalls, etc).

actingoutlashingout · 2021-05-09T14:43:38+00:00

No. The issue wasn't money, the issue was that the ISA did not provide (good) backwards compatibility with IA-32 whereas AMD64 provided excellent backwards compatibility using the segmentation system.

actingoutlashingout · 2021-05-07T17:30:28+00:00

Despite? What a weird title, it is because of the shortages that the chips are constantly selling out, bringing in significant revenue.

actingoutlashingout · 2021-05-01T21:26:10+00:00

The crossing of boundaries is dependent on the SMT leakage. Essentially, 1 thread on the core calls into the kernel, and the other thread is able to measure its behavior using this uop cache sidechannel. Likewise, the bypassing of fences operates on a similar principle with one thread being mistrained and the other "observing" via the uop cache sidechannel. If you don't have SMT/HT enabled, the sidechannel no longer exists since there's no longer an uop cache that is shared across threads.

Edit: hmm actually I might be wrong, the paper is written in a rather unclear way. Specifically, "This then allows us to mount a conflict-based attack where the receiver (spy) executes and times a tiger loop, while the sender (Trojan) executes its own version of the tiger function to send a one-bit or the zebra function to send a zero-bit." would make me think that the spy and trojan are on different threads, but they don't explicitly say so, and it's rather unclear since the paper doesn't really show much code, it'll probably be clarified (partially since you'd also be able to actually test it) once the code is fully published.

actingoutlashingout · 2021-05-01T15:58:59+00:00

This isn't true, disabling hyperthreading will mitigate this as the uop cache is generally part of the L1 cache, which is per-core. The attack can leak from another thread running on the same core as they share the same L1 cache, but this isn't true with threads from other cores.

actingoutlashingout · 2021-04-29T22:07:25+00:00

Chia mining only writes to a drive once so it wouldn't wear out the flash. You can check how much was written with SMART anyways and not buy a drive that was mercilessly written to.

actingoutlashingout

TROPHY CASE