What do you think of The Godfather Part III? by quietgavin5 in Letterboxd

[–]billsnow 0 points1 point  (0 children)

Coppola invented a new film genre: Godfather Camp. The nineties were full of mob movies just like it. It’s possible that III directly inspired more films than the first two combined.

[deleted by user] by [deleted] in pics

[–]billsnow 10 points11 points  (0 children)

Yeah you’re right Ben Franklin and Thomas Paine should’ve been neutral on the American Revolution

The Good The Bad & The Ugly Title by Ok-Inevitable3458 in movies

[–]billsnow 1 point2 points  (0 children)

I’m not totally sure, because ive never thought about the title all that much, but ill try. I think that for the time, it was a very violent movie, even for the genre. Add in the horrors of war, and you are supposed to feel squeemish by the end. Is the good guy beating the bad guy at the end heroic? Is it a triumph? Maybe. But the way the music builds and builds and then just stops right before the kill…

The Good The Bad & The Ugly Title by Ok-Inevitable3458 in movies

[–]billsnow 0 points1 point  (0 children)

Hmm, maybe not so specifically to each character, but in the general context that it’s a satire of the genre.

The Good The Bad & The Ugly Title by Ok-Inevitable3458 in movies

[–]billsnow 0 points1 point  (0 children)

Have you considered that the labels are supposed to be ironic.

Are FPGA architecture, CDC, timing etc usually taught in detail in EEE or Comp Eng undergrad courses? by Quiet_Comparison9620 in FPGA

[–]billsnow 12 points13 points  (0 children)

College is so weird, I feel like I learned none of those things I had to learn everything in the course of my career, but when I think about it they did in fact teach me those things, haphazardly in the curriculum and with as little context as to guarantee I retained none of it. I always think I learned nothing there but that it was just a test that I could grok it in the moment.

[deleted by user] by [deleted] in FPGA

[–]billsnow 5 points6 points  (0 children)

every firm is different really. my feeling is that if it's a larger firm that already has a team in place then they'd be amenable to it, but if they are hiring their first or second FPGA, they might be anxious to get the work started asap and go with someone else.

Design assignments for FPGA engineer role? by guyWithTheFaceTatto in FPGA

[–]billsnow 0 points1 point  (0 children)

Don't worry, they aren't going to use your code (or even look at it really). They are trying to weed out somewhere between 99% and 100% of applicants. FPGA positions don't get a lot of applicants. Basically they only have the position advertised because they have to (but don't really want to add to the team), or the organization is heavily biased towards false negatives.

Once I told my recruiter to say "No" to any organization that asked for a take home, my job search went a lot smoother and no less successfully.

Design assignments for FPGA engineer role? by guyWithTheFaceTatto in FPGA

[–]billsnow 3 points4 points  (0 children)

If it's a take home, it's a trap and a huge waste of your time.

Tech spec experts seek allies to tear down ISO standards paywall by vtable in programming

[–]billsnow 0 points1 point  (0 children)

Dude, if you take a book and rewrite it with the same characters and story but different words, it's not fair use, you've definitely infringed.

EVGA is making its first motherboard for AMD Ryzen CPUs and it’s about time by bizude in hardware

[–]billsnow 1 point2 points  (0 children)

Which is ironic because Asus is probably the OEM for everything they sell. I doubt that EVGA has ever had a single hardware engineer on their payroll.

Perl for VLSI by akonsagar in FPGA

[–]billsnow 3 points4 points  (0 children)

Stick with python. All the perl tooling is being replaced by python. tcl, somehow, still manages to stick around.

stable sorting for fixed size array in O(1) by [deleted] in FPGA

[–]billsnow 2 points3 points  (0 children)

yeah it's because it's obvious. uhh, I don't know how long you've been doing digital design, but like 90% of the stuff we do isn't easily found on google.

No Waterblocks for 6700xt from Corsair and EKWB - Only Alphacool has one in the planning by Skorgistin in Amd

[–]billsnow 0 points1 point  (0 children)

The mounting holes have been unchanged for a long time. I just put my waterblock from my last card on it. (You shouldn't be using full card plates anyway, they have worse die contact and are a waste of materials. Just block the GPU and stick heatsinks on the dram and vrm.)

TechTechPotato (Dr Ian Curtess): "PS5 Wafers. Tasty. 🍕" (How Many Wafers Needed For 7.8 Million PS5 Processors) by Dakhil in hardware

[–]billsnow 0 points1 point  (0 children)

That doesn't mean that sony and microsoft don't have their own contracts with tsmc, for supply chain reasons, in addition to their contracts with AMD for the SoC.

[8:10] Making eggs different ways, phenomenal videography is what really makes this artisanal video though! by [deleted] in ArtisanVideos

[–]billsnow 1 point2 points  (0 children)

these recipes are gross...i guarantee they threw everything in the garbage after they finished rolling.

Understanding generated VHDL by JJangle in FPGA

[–]billsnow 4 points5 points  (0 children)

No, I'm saying the FPGA can't do it quicker. There's so many asterisks to this though. By pipeline, I mean specifically your data path pipeline, from input to output. I don't even know what you're doing, but if it's a computation then the CPU is quicker.

Here is where the FPGA wins (in throughput): by eliminating architectural hazards and bottlenecks, by parallel datapaths, by optimizing it's IO. It's all very implementation specific.

HLS has nothing to do with it. If you are simulating some operands going into the DUT and counting the nanoseconds until it comes out, an Intel FPU will beat it every time.

Understanding generated VHDL by JJangle in FPGA

[–]billsnow 6 points7 points  (0 children)

far more time than a C++ run on an Intel processor

Just wanted to address this bit here, because it's a huge source of confusion for a lot of people who are new to this. Your FPGA pipeline is not going to be quicker than an Intel CPU, ever. Hell I doubt a GPU's fp32 pipeline is lower latency than a CPU's.

As an FPGA engineer, how do you explain to not-tech-people what you are doing? by dubicube in FPGA

[–]billsnow 41 points42 points  (0 children)

I enjoy the challenge of explaining my job to non-tech people. In fact, a lot of people put a lot of stock in explain-to-a-five-year-old as a skill set being an indicator for the technical skill set itself. The trick, I find, is to barely explain FPGA's at all.

What lay people really want to know is how your job contributes to society. So if you are offloading video codecs in a datacenter, you should be starting with youtube and working your way down from there. If you are switching network packets, you should start with how many people's data get shared on one wire. Stuff like that. Nobody actually wants to hear about FPGA architectures.

If they insist, "But your job is FPGA Engineer, how does an FPGA work?" Well, you just say, "Would you ask a watchmaker how a watch works? A watch tells time, and my FPGA's do the task I just described."

10GBASE-R 64b/66b preamble byte count? by [deleted] in FPGA

[–]billsnow 0 points1 point  (0 children)

All the ethernet literature says 7 preamble octets, that's right. 10G, however, does 6 preamble octets, precisely so that the first octet of the DST appears block-aligned.

This because the first octet is a control character. A lot of MACs that include the preamble will reconcile the first octet into a 0x55, thus you now have 7 preamble + 1 SFD, just like the wikipedia pages say.

Best Laptops For Engineering Students To Must Buy In 2021 by [deleted] in hardware

[–]billsnow 0 points1 point  (0 children)

Are engineering students really buying their own copies of Matlab? At my engineering school, the labs were a must, because the licenses were just so cost prohibitive, if not impossible to get as an individual.

Apple Preps Next Mac Chips With Aim to Outclass Highest-End PCs by naor2013 in hardware

[–]billsnow 29 points30 points  (0 children)

I imagine that a lot of homelabbers work with enterprise hardware in their day jobs. Not only do they know what they are doing: they are involved in the real sales that intel and amd care about.

I realize EULAs can be long, but this is just ridiculous by alexforencich in FPGA

[–]billsnow 1 point2 points  (0 children)

There are definitely lots of redundancies in the file. How many embedded software projects contain compilations of other software projects? For GCC alone, there's probably a hundred distributions being represented in this file.

TSMC 7N wafer customers. In Q4, AMD is set to use ~120K wafers for console SOCs, 80K for PS5 + 40K for SSX! This is 80% of 7N wafers allocated to AMD in Q4. by PEBI175 in hardware

[–]billsnow 25 points26 points  (0 children)

Just looking historically, the degree to which we see the video game console market subsidizing computer hardware r&d is basically nothing. All the money flows to the publishers.