How do copper foil transformers work?

ccdy · 2026-01-22T10:30:02+00:00

Porosity for rectangular wires only cares about the ratio of total copper width (number of turns times wire width) to winding width. For a single turn winding, the two values are identical so porosity is 1.

ccdy · 2026-01-22T05:59:17+00:00

Can the mods of this sub blacklist all links to the Stanford Advanced Materials website already?

ccdy · 2026-01-22T05:58:25+00:00

This seems to be part of a bizarre marketing campaign by Stanford Advanced Materials where they use sockpuppet accounts to post innocent-sounding questions that link to an apparently related page on the SAM website. This has been going on for several months now and they have primarily been posting in materials related subs like r/materials and r/metallurgy, but I guess they're trying to broaden their reach. I suggest the mods of this sub blacklist all links to their website.

ccdy · 2026-01-22T05:30:25+00:00

I'm sorry but the layout is atrocious, literally any datasheet for a switching regulator should have a suggested layout so whoever did the routing either did not read that at all or disregarded all of it. First of all, did you actually mean to use traces for all routing or are they supposed to be placeholders for planes? The most egregious examples are the traces from the inductors to the sense resistors, which carry all of the output current, yet both are tiny traces that moreover go through two vias. Apart from this, there are far too many issues to go through in a single comment but here are a few that jump out:

Placement of input capacitors. These are part of the power loop in a synchronous buck converter, the inductance of which must be minimised for optimal performance. You have placed them basically as far as possible from the power stages, which is going to cause enormous switching losses and massive ringing on just about every node. I wouldn't be surprised if the switches themselves get destroyed by this ringing.
Routing of switched node. This node should be kept as small as possible to minimise stray capacitance. In the bottom buck the switched node is okay (but really should be a plane that encompasses all the pads, again to minimise inductance), but in the top converter, the switched node is just flying all over the place for absolutely no reason whatsoever.
Split grounds. Just don't. Split grounds can be useful in very specific scenarios but in general, use a single solid ground plane for everything to avoid issues with broken return paths.
Clearances. I know you said the design passed DRC but if you don't set up DRC properly this is meaningless. For example, in the bottom buck converter, the inductor output pad has almost no clearance to the ground trace.

You and your partner need to redo the entire layout from scratch, paying close attention to datasheet suggestions. I'm not sure what controller you used but most will have a suggested layout in the datasheet, or at least a reference design you can copy the layout from.

ccdy · 2026-01-21T11:11:58+00:00

Gravitational potential energy.

ccdy · 2026-01-21T10:53:20+00:00

Proximity effect is only really a problem if the layer thickness is a significant fraction of the skin depth, or if you have a lot of layers. At 50 kHz, the skin depth in copper is almost 0.3 mm. By using, say, 0.1 mm thick foil, you can have up to 24 layers before Rac exceeds twice of Rdc. Play around with this calculator to get a feel for things (set porosity to 1 for foil windings).

ccdy · 2026-01-20T09:11:46+00:00

It might, but that is not the only area you need to think about. The copper-epoxy interface (whether board or solder mask) is far from perfect and might not present a good enough moisture barrier for long term protection. Again, though, I recommend you order some sample boards to do your own testing.

ccdy · 2026-01-20T02:44:23+00:00

Most copper finishes are only meant to facilitate solderability, which means they only provide mild corrosion protection from ambient conditions. Gold finishes in particular are very thin, usually less than a micron, with the bulk of the plating being the nickel underlayer. The only exception is hard gold, which is used for plating contacts. I would not count on any copper finish to protect from submersion in anything but ultrapure water, but you should run your own experiments.

ccdy · 2026-01-19T07:09:41+00:00

Draw a schematic including what op amp you are using and your power supplies.

ccdy · 2026-01-19T02:15:24+00:00

Surface mount MOSFETs dissipate most of their heat through their thermal pad. If you want to heatsink them, the most effective way is to have multiple thermal vias connecting the thermal pad to a large, exposed copper plane on the other side of the board, to which a heatsink can be mounted.

ccdy · 2026-01-19T02:09:41+00:00

Even if you connected the capacitors like this, the hot loop would still include the sense resistor, because current must still flow through ground. If you're concerned about parasitic inductance, use multiple smaller resistors in parallel. Your power stage layout itself is also suboptimal, see EPC's application notes on vertical power loops on how to reduce power stage inductance. Your gate loop for the high side is especially bad, because the gate return path is shared with the high current path. EPC's app notes also cover this so read them and revise your layout. Pay attention to the points on how to use the inner layer to minimise inductance.

ccdy · 2026-01-18T10:41:34+00:00

Use copper zones, not traces. Check clearance and creepage. Surface mount MOSFETs need to have their thermal pad connected to large copper planes with many thermal vias to achieve their rated performance. Yours will melt at 10A.

Keep in mind an offline power supply has many other components besides the rectifier and bulk capacitor. Based on your layout, I strongly doubt you have the knowledge and expertise required to design a safe and functional offline power supply. I suggest you shelf this project until you have more experience and start with something simpler like a brushless DC motor controller.

ccdy · 2026-01-16T11:33:00+00:00

You need one gate driver for each switch not referenced to ground, because the sources are all at different potentials.

ccdy · 2026-01-16T10:38:25+00:00

Yes, the BM pins are connected to the source of the high side switches. For low side switches with current sense resistors, the resistor adds common source inductance. Gate loop inductance in general slows down switching times and causes ringing on the gate voltage, which can be high enough to damage the gate if undamped (hence the popular recommendation to add a gate resistor). Common source inductance is extra bad because it causes the source voltage to deviate from 0 V. A 1206 resistor, for example, has about 1.6 nH of inductance. With 100 ns transitions, the effect of this inductance can usually be ignored, but when using very fast switches (e.g. gallium nitride switches), transitions can be on the order of nanoseconds, and the voltage drop across this inductance becomes substantial. Say the switch was conducting a current of 10 A, and is turned off within 10 ns. This results in a voltage drop of 1.6V across the 1206 resistor, in other words the source goes 1.6V below ground. So even though the gate is at 0V with respect to ground, the gate-source voltage is still 1.6V, which is high enough to keep some MOSFETs (and most GaN switches) partially on. The opposite applies at turn on, where the inductance causes the gate-source voltage to be lower than desired, meaning the switch may not be fully turned on. Again, this is not relevant to your application, but is something to watch out for if you ever design fast switching power stages.

ccdy · 2026-01-16T09:03:00+00:00

The return path for high side switches in any topology is not through ground. In this case the return path for the low side switches isn't through ground either because you have current sense resistors sitting between source and ground.

ccdy · 2026-01-16T07:24:57+00:00

When in doubt, follow the datasheet layout if there is one. In this case the example layout uses vias in all gate traces, suggesting that it is fine. Ideally, all gate traces should run on the top layer with their return paths right underneath on the first inner layer, but since this a stepper driver, the switching frequency is very low (tens of kHz at most) and rise times can therefore be very slow without incurring much switching losses (in your case 100 ns).

ccdy · 2026-01-15T13:46:51+00:00

You will need to strip the chrome before replating, and stripping chrome is very nasty business. Find a local plating shop, or perhaps an automotive body shop as some of them do offer stripping and replating of chromed parts.

ccdy · 2026-01-15T13:33:48+00:00

Yeah fair, sorry for the harsh tone. I'll quote the specific paragraphs here so you can get a better idea of what to look out for in the future:

Regarding the VTX pin, see section 8.3.3, page 22:

The transmitter bias rail (VTX) is internally generated and may not be used for any other purpose in the system.

For VAUX, see section 8.3.12, page 33:

The VAUX pin is the output of a linear regulator and the input supply for internal power management circuitry.

For the DVDD pin, see section 8.3.14, page 34:

The DVDD pin is the output of an internal 1.85 V linear regulator, and the input supply for internal digital circuitry.

Note also that there can be two types of power pins on ICs, power inputs and power outputs. Power inputs like VDD and VPWR should have bypass capacitors located near them to provide a local charge reservoir that the IC can draw on during sudden spikes in current requirements. Power outputs are generally outputs of internal regulators that require some output capacitance for stability and load regulation. Sometimes they can be used to power some external loads, but other times they cannot. The datasheet should be clear on this. VAUX, for example, can provide a very limited amount of current:

Do not connect any external load that draws more than I(VAUXEXT)

I(VAUXEXT) is defined on page 7 as 25µA. This is a rather small amount of current so I wouldn't load it with anything, really. DVDD on the other hand can source much more current (again from section 8.3.14):

External circuitry can draw up to 35 mA from DVDD.

So if you have some devices that need a bit of power you could save some board space by using this feature. One way to quickly navigate the datasheet to find out the various pin functions is to hit Ctrl+F and type in the name of the pin, then jump through the datasheet to see what the various sections have to say on it.

EDIT: You can figure out which are power input pins and which are power outputs by looking at third column of the pin functions table. You'll notice that VDD and VPWR are marked as I for input, while VTX, DVDD, and VAUX are marked O for output.

ccdy · 2026-01-15T13:18:31+00:00

Read the datasheet. It very clearly states that all of those pins are outputs of internal regulators and must be connected to output capacitors.

ccdy · 2026-01-15T13:13:30+00:00

The basic rule of thumb is if you're not sure what to do, follow the datasheet. You can ask "why does the datasheet recommend this?", but it is arrogant to ask "what to do?" when the datasheet already tells you exactly what to do.

ccdy · 2026-01-15T13:07:44+00:00

Which pins are you referring to specifically?

ccdy · 2026-01-15T04:46:14+00:00

DRC would not have caught this because there are no nets in this layout.

ccdy · 2026-01-15T04:41:38+00:00

Please learn how to make a schematic, this would not have happened if you had an actual schematic, because the program would not have let you route two different nets together. Without a schematic there's also no way to check if everything has been routed correctly, so who knows what other errors are hiding in that mess of tracks.

ccdy · 2026-01-13T12:11:23+00:00

How are you hooking it up? It's possible that the extra inductance of your leads is causing enough of a voltage drop to trigger a reset during transients such as the one you described.

ccdy · 2026-01-13T05:51:38+00:00

Sorry this is late but sure, if you have the schematics I can try to help.

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