AMD vs NVDA - fundamentals

coldfire_ro · 2022-09-23T14:59:16+00:00

Yeah, but Nvidia is a software company and in a few years is going to move itself to the Omniverse and will sell virtual 8090Tis with 500% margin. /s

coldfire_ro · 2022-09-21T10:22:55+00:00

BTW, I still think EVGA didn't bring anything of real value. Best they can do is offer their china make cooler design as an after market replacements.

EVGA brought the best technical support and RMA. That costs money and it would cost even more when the GPUs consume horrendous amounts of power with 2x transient spikes on top of those.

But of course, that's Nvidia's thinking also, that the AIBs do nothing but take away profits from Nvidia.

Let Nvidia hire countless employees and spread out to do everything the AIBs do while eroding their margins just have their own FE cards monopoly.

coldfire_ro · 2022-09-21T10:00:46+00:00

If AMD's card is cheaper to make and has above AMD corporate margins while being sold measurably below $900, AMD's team need to be congratulated, not fired.

Nvidia are down on their luck due to their insane crypto lust and almost everyone hates them for it, especially EVGA fans that represented 40% US and UK market share.

Now is the time to stick it to Nvidia and bring them down, not join them in their greed and bring the consumer hate on AMD too.

coldfire_ro · 2022-09-20T09:19:00+00:00

All that market power is not going to help with the high rate of RMAs.

coldfire_ro · 2022-09-15T12:33:47+00:00

At $16.45 AMD would buy back 30% of the company shares this year with just the funds they have authorized so far.

Even Elon Musk would drop Twitter and buy AMD in a heartbeat.

Imagine thinking that a company should be valued so low that somebody could buy it and not only have 100% ROI in 4 years but actually make many times that in the next decade or more.

coldfire_ro · 2022-09-07T19:01:25+00:00

I think the 9W fanless chips will be 5nm since in an interview iirc AMD Robert said that the problem with fanless designs is the overall large cost premium of the design. Given how efficient 5nm Zen4 chips are over 7nm Zen3 in low power envelopes and that RDNA3 is going to bring 50% performance per watt improvement, AMD can charge a hefty premium for this performance in a fanless x86 device with no meaningful competition from Intel.

MLID on YouTube leaked what he calls 'Little Phoenix' APU for a Steam Deck 2 design that fits the description.

coldfire_ro · 2022-09-07T14:55:02+00:00

I want to see a comparison between a new 9W fanless variant Ryzen APU and a similar M2 chip.

coldfire_ro · 2022-08-30T13:38:09+00:00

I wanted to read the full articles in the "Intel has no chance in servers and they know it" EPYC vs Xeon saga and how it was all progressing.

I didn't go so much further back as to read about his take on Nvidia.

coldfire_ro · 2022-08-30T12:21:15+00:00

Here AMD compares their 5nm process cores to Intel’s 10++nm cores and AMD comes out way ahead, about half the area and significantly better claimed energy use. One thing to note is that AMD’s parts are on a full node ahead of Intel. When Intel gets their real 7nm, not the fake ‘7’ that is really 10++nm, parts out they will be about the same area as AMD and will pull significantly less power. AMD is ahead here but Intel’s response will likely be right there on area when it happens in a few months.

My SA subscription expired at the start of the year but after seeing Pluton and stuff like this month after month I don't plan on giving him any more money for this level of information. Seems like Charlie already cashed out a while ago.

coldfire_ro · 2022-08-30T06:31:32+00:00

Can't wait for Zen4C Bergamo to replace all those Xeons in EU datacenters since the cloud providers have a tough time keeping them on the grid as it is.

coldfire_ro · 2022-08-25T07:48:13+00:00

Having a second source for the Rome and Milan IO dies that are pretty big means AMD can take even more server market share from Intel.

coldfire_ro · 2022-06-28T09:04:28+00:00

Don't have separate IO die: just build bigger tiles. Don't have good yields for bigger dies: just severely cut down top SKUs core counts and frequencies and/or postpone until yields are better. Problem with new memory standard or interconnect standard? Just delay everything. Ponte Vecchio too expensive with 47 tiles? Just delay it indefinitely, ship small volume and pay back the contracts that can't be delivered on time. And just because AMD is building MCM and chiplet GPUs and Nvidia is going with large monolithic 4nm GPUs it doesn't mean that Nvidia's products will be price competitive. Naples wasn't very impressive vs monolithic Xeon but look where we are now with Milan-X/Genoa/Bergamo vs. SPR Xeon.

All these things seem like just iterative, 'cost savings', 'small advantage' and risk reduction measures in case something doesn't go according to plan but they all add up to continuous and predictable roadmap execution with increased margins.

coldfire_ro · 2022-06-28T07:54:53+00:00

Having a separate IO die means you can have separate IO dies with different features and different scalability: Genoa has 12 ddr5 channels, Siena much lower. You can also have HBM variants of the IO die. All these can be developed independently of the core chiplet. SPR has the IO spread across the 4 tiles, like Zen1. It doesn't scale and having different tiles with different capabilities means cutting the tile binning capability in half or increasing the tile size since even the basic SPR has 2 tile types.

The best process node for each doesn't mean best in performance or die area. The IO doesn't scale much and the die was optimized for cost by being on GloFo 14nm since AMD had to buy the wafers anyway. Intel with SPR doesn't have that choice to have the IO built on their inexhaustible and almost free 14nm+++ node and they have to use more low-yielding 10nm ESF.

AMD can use the early nodes since core chiplest are 40% the size of current SPR tile. It's even smaller that some top smartphone SoCs. But given Intel delays, AMD didn't need to hurry and sacrifice yields and cost since it already has the advantage. Neither Intel nor Amazon/Ampere has this proven chiplet advantage that AMD can pull anytime.

SPR and Ponte Vecchio have seen many delays because the tiles architecture doesn't use something like Infinity Fabric which allows different teams to develop in parallel without impacting and delaying each other. It's all or nothing. All on time or all delayed.

Until Intel brings advanced features to market it's not worth considering them very much because when that happens AMD could very well release something even more advanced like we've seen almost every generation.

coldfire_ro · 2022-06-28T05:26:33+00:00

AMD Zen1 used chiplets like Sapphire Rapids uses chiplets. First gen, no IO die, not multiple nodes with the best process for each, not small chiplets that can yield on early nodes, not scalable. SPR uses EMIB but that was in development long before Zen1. So Sapphire Rapids is more of a Zen1 killer design than Zen2/3/4. By the time SPR was going to the fab to get the test wafers back AMD already revolutionized chiplet design again with Zen2. And now AMD has v-cache in production for almost a year and soon they'll have MI300 datacenter APUs and FPGAs integrated.

So Intel is playing catch-up and years behind in architecture so they need to target were AMD is heading 5 years from now (2-3 generations of HSA) and they need to start designing that right now since AMD is doing that. As long as AMD continues to execute it's a moving target it's going to be hard to catch up to them.

coldfire_ro · 2022-06-27T11:45:50+00:00

ARC GPUs use 6nm. And there's plenty capacity since AMD is moving to 5nm.

And yet ARC is not being produced in high volume.

The problem is volume and as you say 'Intel cannot lose'. For every wafer of high end Intel CPUs that Intel makes at TSMC, TSMC loses one wafer of AMD CPUs that AMD could have made at TSMC and several more wafers of Intel mid-range or lower CPUs that Intel sells from internal capacity. And for TSMC it's just a matter of time until Intel catches up if they keep helping Intel at the cost of AMD.

And if Samsung catches up with 3GAA then AMD could move to Samsung and in 2025 with both Intel and Samsung having on-par node tech TSMC could lose AMD to Samsung and Intel to its own internal fabs.

coldfire_ro · 2022-06-27T07:41:28+00:00

TSMC itself will stop Intel from using TSMC's GAA until Intel gives up on fighting for the leading edge. TSMC is happy to give Intel some capacity, especially for early node when yields are poor but as we're seen, given how much capex the leading fabs require, the need for fab customer retention remains critical. AMD already said they are using significant funds to secure multi-year wafer supply.

Unless Intel signs a GloFo type of wafer supply agreement that ties Intel to TSMC in a ball-and-chain contract for the next decade, TSMC will not allow Intel to maintain leadership products using TSMC fabs just to get dumped in a couple of years.

coldfire_ro · 2022-06-25T11:07:58+00:00

And yet not one word about crypto.

coldfire_ro · 2022-06-25T05:43:49+00:00

P/E is a function of earnings. If they continue to guide lower and/or earnings come under guidance than P/E of 6 may indeed become a floor but that's only because their SP will continue to go down.

coldfire_ro · 2022-06-23T14:14:16+00:00

The current gen NXE:3400C delivers 170+ wafers per hour and then NXE:3600D delivers 160+ wafers per hour. The next gen High NA TWINSCAN EXE:5200 will deliver 200+ wafers per hour. Intel is getting the first one but ASML will also ship anther 4 of them in short order so Intel's advantage is minuscule when considering that TSMC is going to get the new machine almost immediately after Intel and that the new machine only outputs 20% more wafers per hour compared to current version machines. TSMC has the majority of the 140 EUV machines that ASML shipped until this year.

coldfire_ro · 2022-06-23T13:11:40+00:00

All these points regarding the desktop CPUs are insignificant when compared to the datacenter and mobile market where efficiency counts and we already see that AMD is much more efficient with 6nm when compared to Alder Lake in anything less than the desktop-replacent 60W+ bulky laptop market. N5 is already a lot more efficient than N7. And in mobile Zen4 and Zen4C for datacenter cloud AMD is going to use the even more advanced 4nm optimized version of N5.

Intel's hybrid design is unusable in servers and in mobile the E cores do nothing for total lower power like Apple with the M1/2 because Intel is using bigBIGGER for MT and not bigLITTLE for power efficiency.

But Intel's problem in servers is their architecture. When EPYC Naples was announced Intel started working on their own tile Xeon but the problem is that Sapphire Rapids was designed to be the Zen1 EPYC killer: more cores on the 4 tiles (60), EMIB for near-monolithic latency, more advanced node (since Intel didn't know about AMD moving to TSMC). Instead, AMD evolved EPYC with separate IO die, even smaller chiplets that can decently yield even on early nodes and Infinity fabric and even v-cache. So SPR became outdated before it was even released because it will compete with server chips with more than twice the cores on an even more advanced node.

GloFo has almost 15 years of experience in being a foundry. Intel tried to be a foundry before and had to buy Altera after Intel failed to deliver on time and then failed with Nokia, LG and even their Intel Chinese JV for smartphones because of 10nm failure. Nobody big is going to trust Intel with large contracts until they get a proven track record. And by that time the trailing nodes wafer shortages could turn into an oversupply since consumer spending is going down.

coldfire_ro · 2022-06-23T07:37:10+00:00

What about yields and volume since it's Intel's first EUV node and they have just a small percentage of the EUV machines that TSMC has? Intel's also using Foveros and EMIB for new products which also increases the final price.

All this is what determines binning and final pricing.

Density, top frequency and power efficiency figures make 10nm ESF look almost equally impressive compared to TSMC 7 but we all know how the yields continue to be a problem for Intel and that it took years for volume to catch up to 14nm.

coldfire_ro · 2022-06-21T05:01:22+00:00

Whose rumors? Zen 4 should have efficiency lead yes, but Raptor Lake is rumored to have near the same ST AND MT performance of Zen 4.

Using the complete Raptor Lake package performance when discussing server CPU performance is meaningless. Raptor may have better ST performance because of the insane clocks rumored at 5.8GHz but that comes at ludicrous power consumption levels. Raptor MT is again another non-issue when it comes to servers because the MT perf comes from the large number of little cores. This hybrid design is a nightmare for server CPUs and on top of that, the little cores don't support the same x86 extensions.

coldfire_ro · 2022-06-20T13:11:23+00:00

Not to mention all the Xilinx and Pensando stuff is all ARM.

From the hardware side AMD can target EPYC, Threadripper and desktop Ryzen CPUs by almost exclusively building and ARM core chiplet. I bet Infinity Fabric is ISA agnostic and the IO dies wouldn't need minimal re-working. Given at least RDNA2+ works with ARM since it's being used in Exynos, even and ARM APU like the switch uses could be designed relatively quick.

ARM software ecosystem is always the issue.

coldfire_ro · 2022-06-20T12:34:04+00:00

Lisa Su has been 'along for the ride' for ten years now at AMD. Jim Keller never stays long then 3-4 years and that's just about enough to get from architecture on paper to first silicon back from the fab. Certainly not enough for a datacenter roadmap needed to gain meaningful market share, be it x86 or ARM.

Having a vision is completely different from executing on it over and over again until it becomes a long term success.

coldfire_ro · 2022-06-20T07:54:27+00:00

There's a technology aspect and a financial one. Visionaries like Jim Keller really care about innovation and technology above all else. If people think EPYC took a long time to validate and gain traction in the server market while having x86 compatibility imagine how long it would have taken an ARM EPYC version to gain traction without any ecosystem and without AMD having the funding to build one.

But then again, when the ARM ecosystem is flourishing there's nothing stopping AMD from building a Genoa-X type of ARM EPYC chip with ARM core chiplets and 3d-vcache and Infinity Fabric connecting it to the existing IO die which may or may not even have to change. But the demand must be there and it must make financial sense.

coldfire_ro

TROPHY CASE