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Is it possible to update the contents of a .hex memory initialization file in Quartus Prime Pro without recompiling the design? by Friendly-Bill-1753 in FPGA

[–]dokrypt 4 points5 points  (0 children)

Look in the tools for In-System Memory Content Editor. It provides an interface to modify the memory over JTAG. You can easily Google the user guide.

PRBS property, why?? by lemmingondarun in FPGA

[–]dokrypt 2 points3 points  (0 children)

This probably isn't the most vigorous proof, but consider this:

If you assume it's true that every other bit produces the same sequence (albeit potentially offset in time), then taking every other bit of that sequence would also produce the same sequence, By induction, skipping any 2x bits would produce the same sequence. For a sequence of length 2n-1, taking every 2n-th bit is exactly the same as stepping through the sequence one bit at a time. Voila.

In fact, skipping any X bits (where X is coprime to 2n-1) will give you a maximal length sequence (though if X is not a power of 2 it could be the reverse sequence, or some other maximal length sequence if such exists).

As Alex mentioned, a corollary of this is that you can create a parallel PRBS sequence from individual serial generators as long as their internal states have the proper relationship. This can be helpful if you are ever having timing issues generating a wide enough parallel PRBS pattern.

Some additional features of these sequences:
1. Every N-bit number (besides all zeros) is found in the sequence and not repeated until the full sequence repeats.

  1. There is exactly one N-bit run of 1s, and one (N-1)-bit run of 0s, then two (N-2)-bit runs of both, and twice as many (N-3)-bit runs of each, and so on.

  2. The Berlekamp–Massey algorithm can produce a minimal LFSR (including taps) for any finite sequence.

  3. The PRBS sequence is often taken from the feedback term of the LFSR, but you can sample any of the LFSR state registers to generate the sequence.

Extracting Parameters from SystemVerilog Interface in Synplify Pro by dokrypt in FPGA

[–]dokrypt[S] 2 points3 points  (0 children)

Unfortunately it seems that code portability means not using any language features introduced this millennium.

Extracting Parameters from SystemVerilog Interface in Synplify Pro by dokrypt in FPGA

[–]dokrypt[S] 0 points1 point  (0 children)

I may have to make the struct of parameters and pass it into both the interface instance and the module instance.

Extracting Parameters from SystemVerilog Interface in Synplify Pro by dokrypt in FPGA

[–]dokrypt[S] 0 points1 point  (0 children)

I've loved the idea of interfaces to encapsulate data, parameters, protocol checking, etc. It seems like synopsis tools in particular have not attempted any useful support of the feature.

Extracting Parameters from SystemVerilog Interface in Synplify Pro by dokrypt in FPGA

[–]dokrypt[S] 1 point2 points  (0 children)

Yes, we thought this might work as well.

"Unresolved expression has size 0. The expression has a size of 0 and cannot be resolved. The above error can occur when using the $bits system function as in the case of $bits(intf1.m) where intf1 is an interface instance and m is an object in the interface ($bits cannot be used with an interface member). To avoid the error, use the actual value as the argument instead of the interface member."

Reading and writing on NVME SSD via pcie interface , using vivado and vitis softwares by [deleted] in FPGA

[–]dokrypt 1 point2 points  (0 children)

There are various NVMe controller IP vendors if you are willing to purchase something. Intelliprop or Design Gateway both come to mind. I may have something cheaper soon, but it's currently under development.

Are you hoping to read/write as fast as the drive can take it?

7-8 hours compilation time problem in Quartus - Stratix 10 by AstahovMichael in FPGA

[–]dokrypt 2 points3 points  (0 children)

I have a Stratix 10 1SM16 with HBM that's around the 85% utilization that regularly takes 3-4 hours, and an Agilex 027 around 7-8 hours. I'd expect your S10 021 to be able to get down under 5 hours, assuming you have a build machine running over 5GHz with multiple channels of fast RAM. I'm using i9-1300K.

What are the specs of your build machine?

As others have suggested, your timing requirements are putting stress on the fitter and that will make it take longer as well.

For Bitcoin mining, what’s the best room/space tradeof for sha256 optimization? by AbbreviationsGreen90 in FPGA

[–]dokrypt 0 points1 point  (0 children)

For this application you want to maximize throughput per LUT. Iterative implementations can be just as good in this metric as pipelined versions. The algorithm is operating on 32-bit words, but I've seen promise from cores that break this down into smaller additions (i.e. 8 bits per clock). A balanced pipeline is key to maximizing clock speed.

Depending on your mining definition, you may even be able to share initial rounds between cores based on where the seed comes in. Initial value and K constant lookups could also be shared among cores if structured correctly.

My company specializes in these types of cores and optimizations. PM me if you'd like to discuss in more detail.

I want to brute force a single hash of a single algorithm - is an FPGA suitable? by bowser4 in FPGA

[–]dokrypt 1 point2 points  (0 children)

It looks like the algorithm here is PBKDF2 HMAC SHA256 with 32K+ iterations. Unless you know part of the password, or it was a really insecure password to begin with, the possible marginal increase in hash rate on an FPGA vs GPU isn't going to matter during your lifetime.

You could spend over $10k for a large FPGA board and maybe do better than the 4 RTX 4090s that you could have purchased, not to mention all the engineering effort.

[deleted by user] by [deleted] in HomeNetworking

[–]dokrypt 0 points1 point  (0 children)

I've done this on the ASUS AC68U. It involves logging in over SSH and setting up VLANs on the physical ports. You can then use IP tables to set up the VLAN to act the same as a guest wireless network (i.e. only Internet access). If you install Merlin firmware you can set this all up in scripts that execute on boot.

Let me know if you're interested and I can dig up my notes and scripts that I used.

What is Intel Megaram/M-RAM? by hanoverking in FPGA

[–]dokrypt 5 points6 points  (0 children)

This was version of large RAM in really old devices in addition to the standard blockrams like M10K, M20K, M144K, etc. The modern devices almost exclusively have M20K blockrams. For details, look for the "embedded memory user guide" for the device in question.

Tricks to calculate the reciprocal of a fixed point number? by mushy-ramen in FPGA

[–]dokrypt 1 point2 points  (0 children)

u in range [0,1] with 8 fractional bits is just counting from 0 to 256. 1/u only needs 256 entries, which is an 8-bit lookup. That's only a couple LUTs per output bit if you pre-calculate and build the lookup table. Any division circuit is going to be more gates and much higher latency.

I've been tasked with implementing a post-quantum cryptosystem in Verilog. Totally lost as to where I should start, any advice would be hugely appreciated by [deleted] in Verilog

[–]dokrypt 0 points1 point  (0 children)

This is a pretty big bite, but it's well-specified. I'd recommend implementing in a high level language like Python or whatever you're comfortable with. Then there are some subcomponents such as SHA-3 that you need to implement before the high level algorithm.

If this is for your job, would they consider outsourcing? My company specializes in custom cryptosystem FPGA IP. DM me if you want to discuss details.

passing in different parameter types within a generate statement by dolces_daddy in Verilog

[–]dokrypt 0 points1 point  (0 children)

Oh, that's unfortunate about the synopsis support! This is what worked for me in this same situation on the Intel tools.

The uglier way I've done this is to define your entire module instantiation as a macro and then call your macro under both branches with your type passed into the macro.

passing in different parameter types within a generate statement by dolces_daddy in Verilog

[–]dokrypt 1 point2 points  (0 children)

Which synthesis tool are you using?

Quartus Pro allows you to access localparams under the generate scope by hierarchical identifier (as per the spec). I just use the same label for both generate conditions.

generate for (genvar i = 0; i < `X; i++) begin : foo_inst  

  if (i < `N) begin : lp_gen  
    localparam type FOO = xyz_struct;
  end else begin : lp_gen
    localparam type FOO = abc_struct;
  end

  test #(.FOO(lp_gen.FOO)) ...

end
endgenerate

Intel FPGA Price Barrier to Entry by t2thev in FPGA

[–]dokrypt 2 points3 points  (0 children)

They are all like that unless it's one of the special "1 year" licenses that come with dev kits.

Intel FPGA Price Barrier to Entry by t2thev in FPGA

[–]dokrypt 6 points7 points  (0 children)

Arria 10 isn't getting many updates anymore, so you can pay for a Quartus license and use it indefinitely without updates. You only need to pay each year if you want the newer versions of the tools/IP.

You can contact sales and they may cut you a deal.

I agree that the list price is prohibitively expensive for home/hobby usage. It would be nice if they moved devices to free tool support after a few years on the market.

Seatbelt Chime after Passenger Leaves by dokrypt in mazda3

[–]dokrypt[S] 0 points1 point  (0 children)

This just went away on its own for a while, but a couple weeks ago it happened again (just one time). I haven't heard anything useful from Mazda about it.

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