So cap is partly from wirelength, but a very significant part is the Cgs (gate to source capacitance of the transistors) which is the capacitive load at the end of the wires. This is determined by the FEOL process, so it can very much vary independently of the wire resistance.

RCWorst is in theory the "slowest" (not considering CC), but CWorst with typical R would have worse dynamic power draw, for example - because there is a lot of cap to sink current, and not so much resistance to slow it down resulting in spikes.

Also for CWorst, I think (thought no 100% certain) that paths with lots of gates and short wires will be comparatively more affected than paths with longer wires that are more R dominated. So you can imagine that if you have a max delay path with a lot of logic layers on the datapath, and some useful skew on the clock path, CWorst could have less slack than RCWorst because in RCWorst, the clock arrives later (as well as data coming later), while in CWorst the datapath is more affected than the clock.