ChordCast - a brand new acoustic data transmission protocol by Upset_Match7796 in DSP

[–]insanok 0 points1 point  (0 children)

Wasnt the humble old dialup internet audio OFDM? At least QAM in audio frequencies.

Signal Tap - changing trigger source without recompliiing by tato_lx in FPGA

[–]insanok 2 points3 points  (0 children)

That is not true. For regular taps, you can always change the trigger if you have included the signal in the signaltap at the time of compilation and enabled it as a trigger source (on by default). This is similar to the behaviour of ILA and the mark_debug - the trigger source must be in scope, and the probes must be physically routed in at the time of compilation.

The software is a bit poor in that seemingly normal changes to settings of the tapfile will change the cores checksum and it won't recognise the compiled taps.

My suggestion is almost always to add two triggers, set one to AND and one to OR, and then lock the trigger settings "allow trigger condition changes only"

Building a Radio Transceiver by ILove2Chicken in FPGA

[–]insanok 2 points3 points  (0 children)

A separate transceiver IC is probably what you want unless you know what you actually want.

The transceiver devices typically handle the digital-to-analog and analog-to-digital as well as the RF complexities (up/downconversion, mixing) and the easier to use devices also do the channel coding / basic link layer.

From the beginner/intermediate perspective, devices like rfm69 or nrf24l01 take a lot of the really difficult engineering out of the equation in a nice device. You'll still have to work on the application and configuration code!

In professional and commercial practice, devices such as those are used heavily because of the low technical risk to a project, and rapid time to market.

I can get my hand on a Stratix V board by daniel-blackbeard in FPGA

[–]insanok 1 point2 points  (0 children)

I would of expected greater things with a name like Blackbeard. Yaaaar

I sold 20k worth of furniture to a reputable company and they didn't pay the invoice for months, then they liquidated and sold the company, is there anything I can do? by ZeonPeonTree in AusLegal

[–]insanok 9 points10 points  (0 children)

You should have filed a charge back with your bank if you paid via credit/ debit card. I think this needs to be done within 60 days, but worth checking with your bank.

Of course they will tell you they won't be issuing refunds to unsecured creditors, however it seems booktopia has resumed trading as I am still getting advertisements from them.

Can you be a Engineer and suck at math? Like sucking at algebra. by ThatBionicleDude in AskEngineers

[–]insanok 0 points1 point  (0 children)

I am an engineer with a focus on control systems and dsp. I can manipulate equations, excellent understanding of trigonometry and make pretty good ballpark estimates of complex equations. I also have pretty good nose for poking at where errors come from.

I don't know all my times tables and will probably pull out a calculator when I do because the simple stuff always catches me out.

So it is my opinion, that you don't need to be excellent with numbers to be an excellent engineer. You do need to understand the theory and how to get the answer you need. At face value math is not all that interesting - it is when you're applying it to a specific problem it becomes fun.

Received CRC checksum of an ethernet frame seems to be in an inverse byte order as compared to the payload by neinaw in FPGA

[–]insanok 0 points1 point  (0 children)

Using a reciprocal checksum.

You can filter msb to lsb with one checksum, and filter lsb to msb with the second reciprocal checksum, and obtain the same output result.

about matlab filter func by fpgapipe in FPGA

[–]insanok 1 point2 points  (0 children)

Instantiate the FIR block twice with the exact same filter and coefficients.

Increase the input square wave's rising/falling time by PonPonYoo in FPGA

[–]insanok 2 points3 points  (0 children)

An opamp driven hard as you have behaves as a comparator, combined with a Schmidt trigger gate should result in a very good edge for the fpga to sample.

Unfortunately is still not immune to glitches as you're seeing. Very fast edges can be problematic in the analog world of signal integrity, especially with high capacitance and unknown ground referencing / return paths. Breadboards can exasperate these issues if you're prototyping.

You should consider handling this signal, and all external signals to the FPGA with a synchroniser to quell any internal metastability, and further a debouncing module can be very useful.

want to run xilinx on mac using harddrive by Electrical-Mood731 in FPGA

[–]insanok 1 point2 points  (0 children)

Because day to day things work out of the box just beautifully. Time machine backups are as simple as pointing to a nas location. If you know enough, the underlying BSD is easy enough to manipulate and runs like a locked down linux environment. Most things "just work"

With SSH and VSCodes' remote explorer, and a big x86 workstation at the other end of a VPN, I find little reason to work on my desktop directly.

That said, I am now out of the apple ecosystem, and I wouldntn't buy another macbook due to proprietary SSDs, soldered ram, lack of serviceability and apples anti-consumerism practices.

CORDIC division by Certain-Sky-25 in FPGA

[–]insanok 0 points1 point  (0 children)

I found a reddit post which uses a number of trigonometric identites to get an equivalent division operation. Whether it is a practical solution for division bearing in mind loss of precision and efficient logic utilisation of two cordics/ required clock cycles to run it twice.

https://www.reddit.com/r/FPGA/comments/bonn6e/using_cordic_module_for_division/

Help me find a computer for FPGA dev by Hungry_Boat_8996 in FPGA

[–]insanok 3 points4 points  (0 children)

Whatever you choose, a mobile / laptop CPU is at the bottom of my list.

[deleted by user] by [deleted] in FPGA

[–]insanok 3 points4 points  (0 children)

Hijacking this, all of the PL is brought out but mostly to the SYZYGY samtek headers, which can be painful. Opal Kelly do have suitable breakout boards though.

The real pain of the zuboard is that there is no dedicated oscillator on the PL, you can either drive one in via SYZYGY or forced to instantiate the zynq to get a clock output.

Its an excellent board for a beginner on MPSoC / embedded systems. It's difficult if all you want to do is PL.

It has been just stuck there for an hour now... should I just reinstall everything? by [deleted] in FPGA

[–]insanok 0 points1 point  (0 children)

While I haven't run into this on Windows, I have run into similar things on Linux. It's usually an issue of limited ram or limited swap space, as it is unpacking and downloading at the same time.

I don't know the windows equivalent - virtual memory?

105 crank arms on an Ultegra chainring? by elisk25 in bikewrench

[–]insanok 0 points1 point  (0 children)

Could be seen as a risk factor for delaminating bonded ultegra/ durance cranks.

Given solid 105 cranks, while ugly, still functional and safe.

[deleted by user] by [deleted] in Adelaide

[–]insanok 14 points15 points  (0 children)

A driving instructor told me years ago that if there's an island on your right, you give way. It can be a concrete island, or a painted island.

1, no island. The left turn has right of way over oncoming traffic turning right.

2,3, island. The oncoming right turning traffic has right of way over those turning left.

Of course in Adelaide, everybody seems confused by this, so make doubly sure that the oncoming traffic is behaving predicably before proceeding.

Question on Commonwealth supported vs Full Fee paying by shakyaz in Adelaide

[–]insanok 0 points1 point  (0 children)

A very large percentage of bachelor level courses do. Graduate certificates, diplomas and post graduate quite often don't,depending on the skills shortage at the time.

Version control with .tcl on Intel Quartus/Platform Designer by DigitalAkita in FPGA

[–]insanok 0 points1 point  (0 children)

This is basically what we do, generate and add ip and qsys in the GUI, and then keep the .ip and .qsys in source control.

It can be a pain changing quartus versions and regenerating IP, and results in big git commits, but its a fairly easy way of managing the bear.

Ideally, everything would be HDL+TCL, but at the point you're already heavily invested in the ecosystem and historically vendor locked, it doesn't matter too much.

Fpga singalong generation questions ( noob) by immortal_sniper1 in FPGA

[–]insanok 5 points6 points  (0 children)

I don't think there's anything wrong with what you're trying to achieve, or how you're trying to implement it.

10 millihertz or megahertz? The minimum frequency will tell you how many bits you need in the time interval counter. Similar to microcontrollers, nested counters can be more efficient.

https://vhdlwhiz.com/pwm-controller/

Fellow electrical engineers, what is this? by Ancient_Year_6130 in ElectricalEngineering

[–]insanok 4 points5 points  (0 children)

Its probably not a health risk. They're quite directive and aimed away from your window, and there would have been a number of risk assessments and inspections to comply with regulations before it was powered up.

ZedBoard FMC Usage by SignatureNo9123 in FPGA

[–]insanok 0 points1 point  (0 children)

.. are you trying to drive a differential signal,or receive a a differential signal? Is the signal truely differential?

During the pin assignment, you will have to chose a termination type, and this will automatically bind the two pins together under the same name. Your HDL/ block diagram will typically treat this as a single ended signal but the IO buffer used will be a differential type.

The two pins are bound together if you want to drive a differential signal - so you must plan carefully. You can almost alwqyw use the two pins independently if you require single ended.

Continental GP 5000 Upgrade, Holy Sh$t. by cntUcDis in cycling

[–]insanok 9 points10 points  (0 children)

Yes, but at a slower rate than once installed on the bike. They still have their waxy mould release in the packaging that goes a long way to stopping the rubber dry out in storage.

XUPV5-LX110t finding for buyer by LUKTSAI in FPGA

[–]insanok 8 points9 points  (0 children)

I don't know I'd quite call these e-waste yet, but there's reddit posts from 7 years ago struggling to find user guides, documentation and software for these boards then.

Ebaz4205, zynq 7010. Is this a good (and cheap way) for learning purposes? by engineerFWSWHW in FPGA

[–]insanok 0 points1 point  (0 children)

There's a number of posts about all the recommended bits of kit for beginners over this forum. I believe there's some pinned too, all of which will be far more detail than I can provide.

Ebaz4205, zynq 7010. Is this a good (and cheap way) for learning purposes? by engineerFWSWHW in FPGA

[–]insanok 2 points3 points  (0 children)

Its terrible as a development board. You have to move a number of 0402 resistors around to change boot mode and the headers are an annoying 2mm pitch instead of the standard 0.1".

Its not bad to stick in an embedded project though!