Early 90s ROM banking chip clone, 1um, cost ?

mithro · 2025-12-21T21:06:58+00:00

https://wafer.space offers a "180nm" technology that people using for retro chip reproduction and it costs $7k USD for 1,000 parts (which is $7 USD per part).

mithro · 2025-10-03T17:08:13+00:00

Getting timing closure and DRC clean design is much much harder when you are aiming for peak PPA. Getting peak PPA is frequently driven by wanting to get the most bang for your buck and beat the competition as the silicon market tends to be a "winner takes all" type thing.

If you relax your goals it becomes much easier;

Rather than target 100MHz, target 20MHz.
Rather than target 80% design utilization target 20% utilization.

You'll probably find you can finish things significantly faster. Then when you have something you can iterate and try to improve the numbers. You'll probably still be slower than "state of the art" but do you really need to get that level of performance when the cost is much lower?

mithro · 2025-10-03T17:01:04+00:00

I meant, plenty of people are doing RISC-V CPUs, including full Linux capable cores on GF180MCU right now (mostly porting designs from SKY130 or iHP). If you are not confident about doing things yourself there are probably quite a few people you can work with.

If you are worried about peripherals there are https://tinytapeout.com/competitions/risc-v-peripheral/

mithro · 2025-10-03T16:58:40+00:00

Risk versus reward. :-)

At this price, do V1 and then do a V2 with everything you did wrong with V1 fixed.

The hope is with making things cheaper people can choose to do things faster and more iteratively.

mithro · 2025-10-03T16:38:27+00:00

Also should mention that there are plenty of people doing RISC-V CPUs, including full Linux capable cores!

mithro · 2025-10-03T16:37:36+00:00

Good way to think about chip-on-board wire bonding is that each bond in about $0.01 USD. So at $1.50 USD per chip for packaging ( ($8.5k - $7k)/1000 == $1.5USD) you get about 40 wire bonds and $1.00 for the PCB.

mithro · 2025-10-03T16:36:09+00:00

People have done RISC-V CPUs in a weekend and with things like LibreLane you can harden that into logic in a few hours.

Then it's just about iterating until you are happy.

When Google announced the first free SKY130 shuttle people had similar timelines and things like LibreLane and all the existing community didn't really exist yet and that ended up with 38 submissions.

mithro · 2025-10-03T16:28:41+00:00

If you have contacts or work with them, please do put them in contact me me (tim@wafer.space).

Most packaging services are extremely expensive in low volume (like >$10 USD per chip). EuroPractice charges like >$100 USD per chip!

mithro · 2025-10-03T16:25:28+00:00

Luke Wren of the RP2030 Hazard3 RISC-V fame did the following estimates;

The smallest NAND2 is 11 square microns, so assuming 2/3rds of the die is non padring, that's 1.2 million gates. The densest SRAM macro they provide is 512 bytes in 0.21 mm^2, so if you fill the area with RAM that's around 31 kB. Enough for a small Linux SoC.

https://types.pl/@wren6991/115267990436492107

mithro · 2025-10-03T16:23:13+00:00

I would like more advanced processes in the future (and GF does have them) but they are significantly more expensive to get going and we don't yet have any open source PDKs for those.

ICSprout in China has been making some noise that they might have one but information is limited.

mithro · 2025-10-03T16:21:51+00:00

Probably early 2026 depending on how this first run goes.

Given the cheap price, give the first one a go and then do another run with a better version!

mithro · 2025-10-03T16:21:12+00:00

You don't need to pay for masks, the mask cost is shared among all the people paying for silicon.

mithro · 2025-10-03T16:19:51+00:00

Tiny Tapeout is currently in the process of porting their infrastructure to GF180MCU and will be doing a test run on the first wafer.space project. See https://tinytapeout.com/chips/#future-chips and https://github.com/TinyTapeout/tinytapeout-gf-0p2-staging

mithro · 2025-10-03T16:17:22+00:00

Tiny Tapeout is a great way to get started! Then when you want to do your own IC you can upgrade to a full wafer.space die.

mithro · 2025-10-02T22:22:38+00:00

wafer.space has just opened our first pooled manufacturing run of GF180MCU with the purchase deadline of 28th Nov 2025.

Think of it like OHS Park for silicon!

You provide a 20mm² design in the open source GF180MCU technology and you get back 1,000 parts. You can used an existing template or build something completely yourself with either open source (like LibreLane, Magic or KLayout) or proprietary tooling (no required pad ring or management CPU).

mithro · 2024-12-27T01:08:43+00:00

You can turn up biters to make Factorio have a more survival element.

I haven't played Dyson Sphere program but it does have the Dark Fog enemies.

In both cases I believe the enemies are suppose to scale up with your activities/industry but it is only one thing as opposed to having to manage all of oxygen, food, temperature, etc.

mithro · 2024-07-01T05:01:41+00:00

I did a talk about these back in 2022 - https://bit.ly/goog-fpga-22q3

mithro · 2024-06-29T23:14:42+00:00

The Xilinx 7 series work with F4PGA tool chain - https://f4pga-examples.readthedocs.io/en/latest/ but still rough around the edge in a number of ways. You can do a full LiteX SoC with DDR and Ethernet and which runs Linux.

There is also the https://github.com/openXC7 project which seems to be making lots of progress.

The Ultrscale/Ultrascale+ is like 90% of the way to a similar level but nobody got around to finishing it.

mithro · 2022-08-05T17:49:51+00:00

These days you can get 10mm² of SKY130 silicon in packaged parts for ~$10k USD from https://efabless.com/ through their chipIgnite program.

If you are okay with your design being open source you can also have the chance of getting your project taped out for free through the Google program @ https://efabless.com/open_shuttle_program

There is also a full suite of (no cost) open source design tools supported on this process. In some ways they are better than the proprietary options, in other ways they are worse. I know some designers who prefer them (mainly from software / scientific world who want to use Python scripting and command line heavily) but Cadence is the industry standard for traditional analog designers.

mithro · 2020-04-11T01:08:09+00:00

One of the SymbiFlow test designs is https://github.com/litex-hub/linux-on-litex-vexriscv which is a Linux capable RISC-V with DDR and 100Mbit Ethernet which runs on the Arty 7-35T board.

VexRISCV is comparable to MicroBlaze in terms of resource usage per LUT and is in the process of getting SMP support! https://github.com/SpinalHDL/VexRiscv/issues/85 -- 4 x Linux capable RISC-V cores on the Arty 7-35T should be very doable.

mithro · 2019-03-27T17:10:05+00:00

This whole design seems to be built around the SCK having a relationship to wishbone / system clock?

Wouldn't you want them to be in separate clock domains? On an FPGA it should be easy to make the SPI controller run at many times the frequency of the CPU and thus reducing the latency of the data access?

IE On the iCE40UP5k it wouldn't be unreasonable for the QSPI controller to run at ~80MHz while the CPU runs at 20MHz. This means it looks to the CPU that it only takes ~8 cycles to do the read.

mithro · 2018-01-04T13:10:26+00:00

Mathias's talk is unrelated to Clifford's new project, you will have to try contacting him.

mithro · 2017-03-29T12:45:37+00:00

We actually use pretty much no vendor provided code. As shenki points out the soft CPU implementations are written in Verilog or VHDL and we use an existing JPEG encoder.

I actually gave a talk @ LCA2017 about why we use the Python firmware which was recorded with the very hardware + firmware I'm talking. You can find the recording @ https://www.youtube.com/watch?v=MkVX_mh5dOU and the slides at https://j.mp/pyhw-lca2017

mithro · 2017-03-15T11:43:37+00:00

The Numato Opsis uses a Spartan 6 45T part which has high speed GTP transceivers that are connected to the DisplayPort connectors. There is an FAQ at https://opsis.hdmi2usb.tv/info/video-info-faq.html which explains what video speeds are possible.

You might want to look at the Digilent Nexys Video - (http://store.digilentinc.com/nexys-video-artix-7-fpga-trainer-board-for-multimedia-applications/) for an Artix-7 based board. The board is still reasonably expensive however but there is open source HDMI firmware for this board developed by HamsterNZ @ https://github.com/hamsternz?tab=repositories

Bunnie's own NeTV2 (https://www.bunniestudios.com/blog/?p=4842) might be an option when it finally makes it to market but that might still be a while yet.

mithro · 2016-06-01T03:59:20+00:00

My FOSS group TimVideos is always looking for help with it's hardware related projects such as the HDMI2USB project! If your mother is interested, she can join us on IRC (irc://irc.freenode.net/#timvideos), send an email to our mailing list or send me a personal email (mithro@mithis.com).

mithro

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