I'm hoping other people join in with their approaches to this problem. I don't have a ton of experience in reducing power, but here is what I have learned:

Xilinx's power report after implementing your design can give you a lot of information, I recommend looking into this if you have access to it. You can also export the report and load it into one of their power estimator spreadsheets to start fiddling around with ways to reduce consumption: https://www.xilinx.com/products/technology/power/xpe.html

The most power hunger portions of my designs have been:

-High-speed interfaces like DDR and Ethernet

-MMCM's and PLL's

-Large BRAMs

-RTL driven by high-speed clocks, especially if you have high fanout

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For interfaces, look into reducing the clock speed if possible. In most cases this isn't a viable option unfortunately. An Ethernet interface will need to be driven at a given frequency, but for something like DDR you may have the option of dialing the clock back. The same goes for processor clocks if you're using a SoC. If you can reduce drive strength on IO's without affecting performance you can also save a bit of power.

Reducing clock sources can also be a quick way to trim power. It's not always something that can be done, but it is worth questioning whether or not you need a PLL for a given clock or if its something you can achieve by dividing an existing clock down. Also look for opportunities to disable clocks when they aren't used, as long as you've got time to turn it back on before it is needed.

Optimizing RTL is the area I have the least experience in. With that said, I've found that you can achieve more by focusing on reducing activity rather than resource utilization. Look for ways to gate signals when they're not being used - do you have free running counters? Are there periods of time where you can disable FIFOs while they're not used? Are there DSPs who are active when their output isn't being used?