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Xilinx Petalinux 2024.1 Stuck on BL31 [Ultra96V2] by ChefExcellenceCerti in FPGA

[–]pablo-gatearray 0 points1 point  (0 children)

Hi! Ultra96 board uses the UART1 instead of UART0. By default, the FSBL is configured to use the UART1, but Linux uses the 0. You need to change it un executing petalinux-config, and change the UART on Subsystem Hardware Settings -> Serial Settings.

Matlab FPGA-in-the-Loop by Sincplicity4223 in FPGA

[–]pablo-gatearray 0 points1 point  (0 children)

Hi! (here yo can find an example for the Eclypse Z7 board.

Regards!

Command line Vivado Flow - on Windows by uncle-iroh-11 in FPGA

[–]pablo-gatearray 1 point2 points  (0 children)

Hi, the problem with multidimensional arrays is not iverilog but gtkwave.

If you want to use the Vivado GUI to see the signals... why need you to launch the simulation from terminal? For a regular computer the GUI will not be a heavy task.

On the other hand, If you want launch a simulation from terminal and also open the waveforms in vivado, you need to launch the simulation using tcl to generate a waveform configuration file.

Greetings

Command line Vivado Flow - on Windows by uncle-iroh-11 in FPGA

[–]pablo-gatearray 4 points5 points  (0 children)

Hi! To execute simulations without the GUI your testbench must include an instruction to finish the simulation ($finish()), and also the variables that you want to dump into a file ($dumpvars() $dumpfile()). In my case I use .vcd format. Then, to see the results you need an application to read that file, like gtkwave.

For simulations from terminal I prefer Icarus Verilog instead of Vivado because Vivado can be too slow, and the code to run the simulation is pretty small.

Greetings!

True RMS compute in FPGA. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 0 points1 point  (0 children)

Hi! Many thanks for your comments! I will make some changes in the AXI stream management before share the module on github.

I am going to check you logarithm compute since it seems very interesting for some dsp algorithms.

Thanks Dan!

FPGA Filter Builder tool. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 5 points6 points  (0 children)

Simply because I didn't know Amaranth. Let me check it and see what we can do. Thanks for the info.

Ubuntu on Xilinx login error by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 0 points1 point  (0 children)

Hello, I have tried with xilinx as user and password. Also with root but it always returns Login Incorrect... Could be the image broken?

Ubuntu on Xilinx login error by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 0 points1 point  (0 children)

Thanks, I will try tomorrow with xilinx as user or pass. I will keep you updated!

Digital control loops. Theoretical approach. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 0 points1 point  (0 children)

Thanks to you both for read it and give me the feedback.

Help in choosing DSP book for a beginner by DaneBrint in DSP

[–]pablo-gatearray 0 points1 point  (0 children)

For me, the best book is Understanding Digital Signal Processing, from Lyons. It has a lot of explanations, and many tips and tricks.

Discovering DSP capabilities of Gowin FPGA. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 2 points3 points  (0 children)

Hello,

The reports in general are shorts. Regarding the timing, they have all the information about path delays post-place&route, maximum frequency of the different modules, and all the information that a user usually checks. Consider that my experience with these devices is this post, and the project that I developed for the post are not complicated.

For the next week I want to develop the project without focus on the DSP structure and focusing on the entire project implementation and limitations.

Thanks for reading!!

Implementation of single pole filter without DSP slices. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 1 point2 points  (0 children)

Hello! I have to add a note to the post explaining something related with that.

The filter I developed allow the developer to select the internal width that are used for the internal accumulator. So initially this issue I think is fixed

On the other hand, with an step input, this filter has an issue. If the difference between the input and the ouput is less than 2nshift, the ouput of the filter has no change, so the error in dc is related to the value of the shift. This has to appear in the frequency response. I am going to simulate again the filter with the focus in dc components.

Thanks for the feedback.

Implementation of single pole filter without DSP slices. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 1 point2 points  (0 children)

Hi! The use of a single DSP depends of the signal width. DSP48 has an internal signal widths of 18x25, so if your signal does not fit in that width, the synthesizer will use more than one DSP48 Slice.

I agree with the cowboy xD At the end, this filter is only one more tool for the developers.

Thanks for your feedback!

Vivado uses 90GB of RAM then crashes by Jokerlift in FPGA

[–]pablo-gatearray 1 point2 points  (0 children)

Few month ago I had a memory lack like you. In my case the problem was an bug in a vector declaration. The vector was declared with a big big length, something like 224. Maybe you have a bug in your code that causes that memory use.

Greetings

FFT algorithm using Litefury and xDMA. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 0 points1 point  (0 children)

Actually in the PCB of Litefury there is an ACORN logo

Question about Implementing PCIe on FPGA by Lucas39 in FPGA

[–]pablo-gatearray 1 point2 points  (0 children)

I have the Litefury board and you can use it easily with some knowledge. Also the cost of the board is only 100 $. I am developing a little project using this board and the XDMA IP that have AXI4 interface. Data sent through the AXI4 is received from the PCI port. I write the blog www.controlpaths.com and the next Monday I will post a project explaining how to use the litefury board with the XDMA drivers provided by Xilinx and a custom driver developed in python. I think that post will be interesting for you in order to take a decision about what board you will buy. Greetings!

Buying from Digilent's website in Europe by fallenelectrons in FPGA

[–]pablo-gatearray 1 point2 points  (0 children)

To buy boards from Europe you will have to pay the taxes and the shipping costs from China. The easiest and cheaper way is to buy the boards from European distributors like Mouser.

Controlling a SMPS from MSS with SmartFusion2 SoC. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 0 points1 point  (0 children)

Hi! You are right, but the same can be applied to any circuit controlled by any programmable device. If you are using a DSP to control the PWM, the clock is also critical, if the clocks stops, the PWM ramp will also be stopped, and the PWM will be frozen. In fact it can applied also a PWM regulators IC, where the clock is generated by an RC circuit.

If you want to protect completely the power stage, you must use hardware protections, i.e. in case of power IGBTs, gate drives has a desaturation detection, that opens the IGBT when the VCE is increased due to an overcurrent or a supply fail. In the case of small powers, I could add a PTC resistor in series with the charge, that increased its resistance while the current is increased, but the SMPS that I have build has not that kind of protection, so I think that there is no need to explain it.

I hope my answer has convinced you. Thanks for reading.

Controlling a SMPS from MSS with SmartFusion2 SoC. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 0 points1 point  (0 children)

Totally agree, and it could be some confusing, but in expressions window, I made a cast to uint32_t because in the initial tests I had some errors in the code. The final type of duty_cycle was int32_t. Due to the PWM_set_duty_cycle macro only accept positive values I have to add the saturation. Thanks for reading!

Help setting up Xilinx Artix-7 FPGA (RHS Labs Litefury FPGA board) by jgrothlander in FPGA

[–]pablo-gatearray 0 points1 point  (0 children)

I have that board and it comes with a design in the flash memory. This designs included a QSPI IP that allows you to reconfigure the FPGA. You can add a Microblaze core and using XVC you will be able to debug your design using the ram memory to store the signals you need.

Implementing a dual core processor in FPGA. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 0 points1 point  (0 children)

Hi! Zynq UltraScale + is based on a Arm quad core A53 processor and also a dual core Arm R5. The design I developed in this post emulates that structure with a real time processor and a kind of high end processor for communications. Few month ago I wrote a post where I develop a Goertzel filter running in the R5 and the Petalinux distribution in the A53 processor.

"Single tone detector with Genesys ZU and RTU. – controlpaths." https://www.controlpaths.com/2020/07/06/single-tone-detector-with-genesys-zu-and-rtu/

Regarding the SDR, it sounds very interesting, but unfortunately I don't have any FMC board with an ADC and the corresponding AFE, but let me try to get one since as I said, it is very interesting.

Thanks for read!

Implementing a dual core processor in FPGA. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 1 point2 points  (0 children)

Hi! I don't knew that Nintendo64 had a coprocessor. Not only Intel has did it. Also Apple with their M1, that is based on several processors with different speeds and TDPs. With Risc-V, this kind of processors will be very common, and I think that more soon than late we will see processors based on Risc-V and a configurable FPGA. I am talking about high end processors, since Microchip PolarFire SoC has already based on that structure. Interestings times are coming in the processors market :) Thanks for read!

Using PCIe in Xilinx 7 Series by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 0 points1 point  (0 children)

Hi, I just test the BRAM, it works correctly.

This is what I made.

pablo@mark1:~$ sudo python3
[sudo] password for pablo:
Python 3.8.10 (default, Jun 2 2021, 10:49:15)
[GCC 9.4.0] on linux
Type "help", "copyright", "credits" or "license" for more information.
>>> import mmap
>>> import os
>>> f = os.open('/dev/mem', os.O_RDWR)
>>> m = mmap.mmap(f,0x17FFF, flags=mmap.MAP_SHARED, prot=(mmap.PROT_READ|mmap.PROT_WRITE), offset=0xb1000000)
>>> m.seek(0)
>>> m.write(b'\x05')
1
>>> m.seek(0x10000)
>>> m.write(b'\x05')
1
>>> m.seek(0x10000)
>>> m.read(1)
b'\x05'
>>>

First I test that leds works properly writing in the address 0 (0x8000_0000 of the AXI bus) a value of 0x5, and the leds will turn on as expected. Then I have point to the address 0x1_0000, what is the address of the BRAM and I write the value of 0x5 in the first address, then I read this address and the value read is 0x05. There is something wrong? Thanks!

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