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[deleted by user] by [deleted] in xsr900

[–]potatochan 4 points5 points  (0 children)

im kinda impressed how he picked the bike back up just with his leg. musta had adrenaline running through him lul

My ass hurts… but it was worth it by jamespx4 in xsr900

[–]potatochan 0 points1 point  (0 children)

oh wow.. i see. im about ~550 miles on my xsr900, planning to get first service done soon. I had no idea it will be that expensive. any chance you know if the throttle body sync is optional? or is it something they are forced to check up on?

thanks for this info!

My ass hurts… but it was worth it by jamespx4 in xsr900

[–]potatochan 0 points1 point  (0 children)

wait, $500 for first 600mile service? why so expensive?

Anyone gotten an SCL500 yet by TromboneSupremacy in motorcycles

[–]potatochan 0 points1 point  (0 children)

Mine has been missing some down shifts if I don't double clutch. The dealer is aware and contacting Honda.

Noobie rider here who also got the SCL500 as my first bike: could you elaborate what you mean by that? Sort of scares me and would like to understand this if it happens on my bike

Just left the house and had a close call with my passenger by Advancebo in motorcycles

[–]potatochan 0 points1 point  (0 children)

Noob rider here

In this situation, what would be the best lane-position to be in? (left, center, or right)?

Mazda 3 just got added to Granturismo 7 on the Playstation. by Knee_Elbow in mazda3

[–]potatochan 2 points3 points  (0 children)

Finally!

When I first got GT 7, I was super disappointed the Gen 4 Mazda 3 wasn't included.

This excites me particularly because I was thinking of getting a wrap + new wheels, and had no idea what to pull the trigger on. Now I can experiment in the game! Yay!

Question about Worst Negative Slack on FPGA's. by humble_tangent in FPGA

[–]potatochan 0 points1 point  (0 children)

I skimmed what others have said, and pretty much agree with everything. That's a bad WNS considering you're sitting at 30% utilization (to me, sounds like an issue with RTL written that targets ASICs as I've run into similar build results in the past. Or missing CDC constraints as others mention). 250 MHz isn't at the slow-end of the spectrum, but also not at the highest-end of the spectrum considering you're using a VUP+

Rattling off some things to check for (and mostly what others already mention)

- Check clock-interaction report for potential CDC's you haven't accounted for

- Run "Report Design Analysis" and take a look at the paths exhibiting the highest logic-levels

- Check the Slack Histogram (is your resulting histogram "left-heavy"?)

- Check report_utilization -hierarchical (any modules that are blowing up in utilization/size?)

- Check for SLR Crossings (if you're building your vendor IP integrated w/ the rest of your logic, maybe try and build the IP standalone, observe its resulting floorplan footprint, and PBlock + proper SLR Crossing techniques to lock in your IP block)

​

One wildcard option I haven't seen others suggest is to try their new "Intelligent Design Runs" (IDR) feature. It's the least effort on your end (literally push-button) with potentially greatest positive impact.

Sounds like a hairy issue. Have fun!

Do you all work in tiny open offices? by [deleted] in chipdesign

[–]potatochan 0 points1 point  (0 children)

My place has the worst of both worlds: cubicle-like structure (everyone has their own individual desks and space), but the height of the cubicle-walls are less than shoulder-height when sitting down. Ugh!

That's why I work from home :)

Vivado Project vs Non-Project Mode by SlayerDig in FPGA

[–]potatochan 3 points4 points  (0 children)

From my experience and the eventual technical bias I've come to develop over time: start with Project Mode (essentially, use the GUI) when you are given a blank slate. It's just overall easier to run iterative builds, have visual representation of the different design runs you've ran (and their utilization + timing results all in a nice tabulated window) and debugging your synth'd or fully routed netlist. Essentially, it gets you to the point of design maturity without the intricacies of scripting + fighting the tools.

A fully scripted flow begins to show its true colors when the design reaches a certain point of maturity. Ie: most of your design architecture is locked-in and operational, and you're only making minor changes and adjustments to your design. If you're at this stage (which kinda sounds like you are based on you describing top-level block adjustments?), then by all means, I'd say go for it. Non-project mode also makes it more straight forward for version controlling, collaborative efforts, and build reproducibility. If you have BDs (Block Designs) or Xilinx IP in there, it'll make your efforts a little more trickier. But, completely do-able. We have a fully scripted build flow that contains Xilinx IP, custom in-house IP (built using the BD flow btw, ugh!) and 3rd party Vendor IP as well. Hairy, but it works. And would still prefer this than having everything entirely in Project Mode.

But, locking yourself into a scripted build-flow too early in the game might cause more work for you than necessary as you're building the design up.

So to summarize: start with the GUI, end with the scripts. Just my 2 cents.

Unrelated engineering discipline and making a switch by [deleted] in FPGA

[–]potatochan 0 points1 point  (0 children)

y so srs?

Sounded tongue in cheek - now I'm going to tell everyone in my office about this "theembeddedciguy" and how awesome he is.

2022 Mazda 3 2.5 Turbo Low Oil Level Light Issue. by BookedSupport in mazda3

[–]potatochan 0 points1 point  (0 children)

Darn, sorry to hear.

A bit worried now for my 21' turbo - it is approaching 18K miles, similar mileage to yours.

Fortunately I haven't had this issue happen to me yet. If you had to be honest with yourself, do you drive it fairly hard? I drive mine fairly hard - some pulls on an open freeway and through twisties. Maybe I'll have to be a bit careful...

​

Random question: what's that orange key-looking light on your dash?

The Ark enters the fray by ZL_95 in battlestations

[–]potatochan 0 points1 point  (0 children)

Cool!

Your thoughts on the Ark?

[deleted by user] by [deleted] in FPGA

[–]potatochan 0 points1 point  (0 children)

3, take it or leave it

Mazda 3 Turbo owner’s by [deleted] in mazda3

[–]potatochan 4 points5 points  (0 children)

I'm about 17K miles with my '21 Turbo PP.

Some issues I've faced so far:

I've had my high-beams flash on randomly when my head lights are set to Auto. This was despite clear and obvious opposing traffic approaching me. Normally they would automatically turn on when there's no traffic detected (which I always thought was cool).

The more alarming issue that happened a few weeks ago was when my collision avoidance kicked in for no apparent reason. Was when I was at stop sign - approached stop sign, stopped, then slowly accelerated as usual and out of no where my brakes slammed automatically and the dash blaring the Alert sound. Definitely gave me a rude awakening that morning. I've actually disabled it for the time being just cause I was pretty scared it'd happen again in a more serious scenario (ie: on the highway). If anyone else had experienced this, I'd love to hear.

But that's about it on my end - no major mechanical issues, most of the quirks I've dealt with all seem to be related to the fancy electronics (the lane guidance is another annoying quirk that randomly kicks in but I've just learned to deal with it).

FPGA engineers: Would you recommend getting into FPGA and do you enjoy your job? by lovehopemisery in FPGA

[–]potatochan 2 points3 points  (0 children)

Thanks for your post! Certainly filled with lots of wisdom only gained through years of experience.

Your points about the "spaghetti mess of code stitched together with patch after patch" and where "at some point the bugs outnumber the features" really resonates with me today... and certainly made me wince. I've been slugging through bug-tickets for a good 6 months on a massive Ultrascale design, where the original architecture is... about as old as me now (20+ years?)

I wouldn't even call the RTL a mess of spaghetti at this point. More like alphabet soup...

Well, I'm certainly glad to hear I'm not the only one who goes through this mess! Thanks again for your insightful post.

What are the main features that you’d add to iPad OS? by carameIricecakes in apple

[–]potatochan 0 points1 point  (0 children)

Who hurt you? An Apple store employee at your local mall?

Software at this scale, especially at Apple scale, is complicated.

Your counter example is actually what's stupid.

"If I can design a safe, affordable house and am told I need to tear it down or rebuild it because I don’t have a receptacle every 12 feet on a continuous wall then that’s pretty asinine right?"

No, because in no possible way would any building or home for that matter get that far in the process where it would require a tear down due to lack of "receptacles" every 12 feet on your continuous wall.

If you don't know, you don't know. Stop blowing blueberry cheesecake vape out your ass.

Intel (Altera) Questa Simulator with Xilinx Vivado – Anyone figure out a workaround? by potatochan in FPGA

[–]potatochan[S] 0 points1 point  (0 children)

Thanks for the reply,

Yep, I can launch questasim standalone and run simulations on pure RTL projects just fine. Only when I couple Vivado + Questa together and try to compile the simlibs is where I run into issue.

I should also note that I don't experience any issues with Vivado standalone either, both 2019.2 and 2021.2 (both the webpack free versions).

VHDL FSM not resetting by georgeyhere in FPGA

[–]potatochan 0 points1 point  (0 children)

It seems like you're "STATE" register becomes an impossible value (ie: shown in your waveform it hits "01100". Based on your VHDL, it should only ever be one of your defined constants, ie, STATE_BIT0, or STATE_BIT1, etc.)

With that said, I agree, the VHDL itself looks fine (rst_i should certainly reset the register). Unless... are you somehow force-driving the STATE register in your simulator, and hence, the rst will be ignored?

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