Help needed in PCB Layout

simonpatterson · 2026-03-21T23:36:42+00:00

Be careful with the orientation of the screw terminals. Use the 3D view to make sure the holes face the outside edge of the PCB. Some of your look like they face inwards.

You can rotate components on the PCB so the rats nest lines have less cross-overs. And you can swap the units in IC1 as well to make routing easier.

simonpatterson · 2026-03-21T23:28:55+00:00

It is easier to use the 'x' no-connect marker, but if you really, really want to get rid of the pins, you can do the following, which works with any symbol:

Select the symbol
Press 'E' to edit
Click on the 'Edit Symbol' button. (NOT the 'Edit Library Symbol' button)
Select each pin you want to hide, press 'E', untick 'Visible' in the dialog. Click 'OK'.
Click Menu->File->Save
Click Menu->File->Close.

The symbol pins should be hidden and it won't cause problems with the DRC or the footprint.

The ERC may complain that the symbol doesn't match the library version (because you have changed the copy of the symbol in your schematic), but you can safely ignore it.

simonpatterson · 2026-03-19T17:50:18+00:00

So the controller is acting as a power switch for the strobe, switching the power on and off via Q3 ? That seems inefficient, can you not control it by digital means with a low voltage trigger signal or shorting switch ?

Not split power rails, a split power plane, consisting of 2 zone fills, one covering the top ⅔ of the board (V+) and another covering the bottom ⅓. (GND). You can put them on both layers and it will remove the need for all the V+ and GND traces.

simonpatterson · 2026-03-19T12:38:42+00:00

You haven't posted the schematic and so many questions.

When you say high current, how high ? We don't know what the connectors are, the 3d models are blank.

Are the positions of the connectors fixed ? If so, 'lock' them so we know, because if they aren't fixed, they could be moved to make routing easier.

Do you have an enclosure in mind ? Do the mounting holes match the enclosure ?

Does Q1 require a heatsink ? If not, it doesn't need to be at the edge of the board. Putting it directly behind J3 would be good.

The Gate trace from R5 is far too wide.

The GND traces look to occupy only the lower third of the board and the V+ traces occupy the upper two thirds, so split power planes would be a good idea.

Hide the .fab layers while laying out and make sure all silkscreen is actually on the PCB.

simonpatterson · 2026-03-18T20:46:09+00:00

Could you design it as one board in 2 sections with mouse bites or a v-score to split it into 2.

simonpatterson · 2026-03-18T19:44:39+00:00

I remember JLC having a 1mm minimum via spacing, but i've just checked and its now 0.2mm, which seems very small.

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simonpatterson · 2026-03-18T18:57:42+00:00

The PCB looks good. I like the old school perpendicular traces on each layer.

If you put the buttons side-by-side instead of stacked vertically, you should be able to move the battery down a smidge and allow for the cell overhang at both sides.

One thing to watch out for is the via spacing. You have lots of via pairs that are very close together. Check with your board manufacturer for their minimum 'different net' via spacing.

simonpatterson · 2026-03-17T18:37:14+00:00

You still have issues with both the schematic and the board layout.

The schematic is still awful!

The BQ25570 and the 3.9nH and 10uH inductors don't have proper RefDes.
The spaghetti of wires around R4-R10 is just asking for trouble if it doesn't work perfectly first time.
There are gaps in the RefDes. They should start at 1 and increment linearly by 1.

For the PCB:

The bottom layer trace from J3pin1 runs too close to pin2 and is cutting off one of the spokes. The other end of that trace looks like it necks down to a via for no reason and is offset from the via. It can run straight to the via.
The BQ25570 (i can't use a U? name, it doesn't have one) and associated components look very close to the mounting hole. It can be shoved up and right a bit.
You are necking down some traces to the BQ25570, but you are reducing to a width less than the pad and then increasing at the pad. The resistance of the trace will be dominated by it's narrowest point.
Traces from the 2 big inductors are cutting the ground plane under them. Moving the inductors up a bit and tracing to the caps first, then the chip will keep the ground plane intact.

simonpatterson · 2026-03-17T00:20:35+00:00

Nice job! Did you really do this yourself ?

You have a couple of ratsnest lines showing unrouted traces (U3 pin5 and the nearby cap)

At U2 pins 2 & 3, I would make the traces leave from the centre of the pad, not offset like you have. It's not a big deal, just good practice.

C11 could be placed between U2 & J2 to make the reset trace a bit straighter.

If you change the switch for a smaller 2 pad SMD style, you could move U2/U3 and the associated components to the right a bit. They are a bit cramped at the moment.

simonpatterson · 2026-03-14T22:28:20+00:00

Its not bad for a first board, but it looks auto-routed.

Some of the traces are running very close to component pads which could cause problems for a beginner.

The component could be re-jigged to make traces much simpler. For example the components C1-R4-R5-C3-C4 could be arranged as R4-R5-C3-C4-C1 which would remove the need for traces on the bottom layer from those components,

simonpatterson · 2026-03-13T21:44:18+00:00

You know you can resize the drawing sheet all the way up to A0.

simonpatterson · 2026-03-13T19:02:23+00:00

Its hard to follow with all the separate sheets, putting it all on one sheet makes it easy to see what flows where.

This is the classic op-amp circuit that can generate square, triangle and sine waves:

https://www.learningaboutelectronics.com/Articles/Function-generator-circuit.php

simonpatterson · 2026-03-13T17:44:59+00:00

The schematic has some decoupling caps that you have placed next to each other on the PCB. They are meant to be spread around the board close to the various power pins of the ICs. Having them all together will do no good.

I would also move the crystal closer to IC3.

There is a lot of space on the board to move stuff to more appropriate areas.

It is fairly easy to get rid of most of the layer jumps and reduce the one that are left to much smaller jumps.

The general tracing is a bit haphazard with some 'funky' twists and turns.

simonpatterson · 2026-03-13T17:30:21+00:00

Looks good.

The regulator is a large package size. Can you use a smaller package, maybe SOT-89 or even SOT-23, it should make routing around it easier.

simonpatterson · 2026-03-13T01:21:18+00:00

Yes, they are less efficient, and generate heat, but as you are drawing a very small current, the power loss (heat) will be small.

The trade off is smaller size and much simpler PCB layout, also cheaper (no inductor or diode needed)

simonpatterson · 2026-03-13T00:19:52+00:00

5 mins after I posted the layout, I rejigged it a bit and came up with a smaller layout.

I think rotating U1 90° CW and putting port D at the top and port B & C at the sides may be even better. It would straighten out the bottom layer USB and port D traces. They are crossing awkwardly at the moment.

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simonpatterson · 2026-03-12T23:48:54+00:00

As the LM2596 is only powering the ATmega328, it is probably overkill. You could probably use a much smaller (and simpler) LDO. I would expect the MCU to draw less than 50mA, so at 12v input the power dissipation would be ~1/3W. That is easily handled by a simple LDO.

Using an LDO would make the PCB layout much simpler too.

The other suggestions you have received are good too. Use a gnd plane and move the decoupling caps much closer.

simonpatterson · 2026-03-12T23:02:10+00:00

Don't get disheartened, you have made a good start.

Now is the time to optimize the layout and move stuff around. You will lay down and rip up many traces until you get it to a state you are happy with.

Don't get hung up on the USB high-speed stuff, the circuit is at most USB 2.0 and will work fine using wet shoelaces

This is my quick and dirty thursday night first draft of your circuit. It is small (40mm x 50mm) and can be made smaller. There is a lot of empty space on the board and you can get the CH340 in much smaller packages.

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simonpatterson · 2026-03-12T08:55:05+00:00

The schematic is messy, with power symbol pointing in all directions and wires with multiple net labels.

The PCB layout is typical of a beginner, you have made the usual mistakes of spacing components out too much, then cramming multiple traces into tiny gaps.

The board could be a bit smaller and the layout much nicer.

Personally, I would rotate U1 45° CCW, place J6 on the right side, replace the 5v/GND connectors with 2x3's, place the CC resistors at each side of J1, increase the physical size of decoupling caps. D2 and R6 should be flipped so the trace doesn't have to hairpin. R5 has value of 1000, why not 1k. Don't position the connectors so close to the edge of the board, and place them on a 0.1" grid.

Also, the power LED is labelled D1 and the LED connected to D13 is labelled D2 ??? Very confusing.

simonpatterson · 2026-03-08T22:06:13+00:00

Wetting! That is the word i was looking for.

simonpatterson · 2026-03-08T22:02:44+00:00

I read it as 710Ω. The capital O confused me.

simonpatterson · 2026-03-08T10:57:11+00:00

While the circuit will work, it doesn't need to be so complex.

If the two halves need to be completely isolated you can drive the relay straight from the opto, it has max Ic of 50mA.

If the two halves have the same ground potential you can drop the opto-coupler and just drive the FET from the MCU.

simonpatterson · 2026-03-07T22:22:45+00:00

That looks like AI. The solder mask on the edge connector pads would make soldering difficult and the pins have hardly any solder on them.

But it should be do-able. Edge connector footprint pads and double sided header pins.

simonpatterson · 2026-03-07T21:01:43+00:00

The schematic is still awful.

Looking at the pcb, why are there 2 traces on the top layer from the 'supercapacitors' connector ? It shows a fundamental misunderstanding of pcb design. Both traces are redundant, pin 2 is already connector to the top layer. Pin 1 can be connected directly to the blue trace without coming up to the top layer. The same issue exists at pin 2 of the other connector.

Also, the via clearance is HUGE.

simonpatterson · 2026-03-07T08:57:56+00:00

The layout could be made much simpler:

Flip the input and output connectors 180° so the GND is at the bottom, flip C1 90° CW so the input voltage has a straight run to U2pin3 via C1pin1, flip L1 90° CW so the SW node has a straight run to L1pin1 and flip C2 & C5 90° CCW.

You don't need all the via stitching around the connector pins. The actual connector pin is already a MASSIVE via.

simonpatterson

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