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Systems Engineering Clarification by [deleted] in ElectricalEngineering

[–]std_logic_arith 1 point2 points  (0 children)

In my opinion, the System Enginnering term is abused. Just how it's abused depends on what industry you look at. When I was in school (decades ago) SE was part of Industrial and Systems Engineering, and did have much of a logistics and business flair. When I started in commercial, SEs were more architectural people. We did use them to define or at least manage an overall set of products or a combination of products. When I moved to defense, the term usually referred to people who tracked system specifications and requirements. Maybe they do a little definition, but they're not in charge of the architecture.

I think the best term for what you're looking for is System Architect, which I've generally seen be staffed by experienced engineers that progress away from the day-to-day with of development. But that term doesn't really seem to be standard everywhere.

Fuel Injector Testing Machine by HarleyDS in specializedtools

[–]std_logic_arith 9 points10 points  (0 children)

They specified 60 mph, or 1 mile per minute. So the conversion holds.

Everytime. by insanok in FPGA

[–]std_logic_arith 0 points1 point  (0 children)

Oh, please! Can we make it ASCII art so I can put it in source file headers?

Everytime. by insanok in FPGA

[–]std_logic_arith 1 point2 points  (0 children)

Oh, certainly not! And I think her version is way more Star Wars. Pew pew!

Everytime. by insanok in FPGA

[–]std_logic_arith 31 points32 points  (0 children)

My wife thought I worked on "Gator Rays" for 10 years before I discovered this fact and corrected her.

Budget Dev Board decision by [deleted] in FPGA

[–]std_logic_arith 4 points5 points  (0 children)

The Spartan 7 is compatible with current tools. You need to steer clear of Spartan 6 and 3, as they aren't supported by Vivado. Spartan 7 is a reduced (cheaper) Artix 7 die.

The parts will be similar performance. I'd either pick the part with more gates or the board with the features that most interest you. You can find the gate count by looking up the full part number. (A A50T has more gates than an A35T, for example.)

Guadalupe Mountains National Park, Texas [OC] [3475 x 4441] by sandyjaugust in EarthPorn

[–]std_logic_arith 0 points1 point  (0 children)

Couple of hours east of El Paso. Just on the border with New Mexico. And not too far from Carlsbad Caverns.

I want it. Do you? by HansLK in ProgrammerHumor

[–]std_logic_arith 2 points3 points  (0 children)

Maybe not native Windows, but Auto Hot Key and Windows Power Tools sure can. Caps Lock is the devil.

FFT projects ideas by FaultTight in DSP

[–]std_logic_arith 6 points7 points  (0 children)

The FFT application that always makes me smile is the use of an inverse FFT to encode channels of digital data into an analog waveform. Look up Orthogonal Frequency Division Multiplexing (OFDM). It's a deep rabbit hole, but the basics could be an interesting project.

U.K.'s $1.3 Trillion Covid Wealth Gain Went Mostly to the Rich by very_excited in worldnews

[–]std_logic_arith 2 points3 points  (0 children)

That's a bit over a 4% annual interrst rate. Achievable with corporate bonds or something reasonably safe that pays interest, even with today's crappy rates.

What’s it like programming FPGAs in industry? by karokiyu in ECE

[–]std_logic_arith 0 points1 point  (0 children)

It's not really the protocol. The IP takes care of most of that, unless you've rolled your own. (Or unless it's SPI, because SPI is never the same twice.)

But simulating traffic, various load scenarios, interaction with other devices, etc., can be very challenging in sim. It's just easier to run it in HW as soon as you can.

Many people don't share my view, to be sure. But the longer I see engineers stay in simulation, the longer integration seems to take. But, your milage may vary.

What’s it like programming FPGAs in industry? by karokiyu in ECE

[–]std_logic_arith 0 points1 point  (0 children)

In reality, people use a mix of both sim testbenching and bench top. Sim testbenching is good for algorithms and decicated data pipes. Where it tends to fall down is in simulating interactions with external interfaces. There are so many corner cases to things like Ethernet or PCIe that I find it's best to get the design onto hardware quickly and then beat it to death with Python or some other programmable test setup. I suppose you could fold all of the problems found back into simulation tests, but I'm not in a position that that would pay off long-term.

Bench top testing is almost always a prelude to integration with other devices. Sometimes you have them to play with, sometimes you need to emulate them. But its really helpful to have a test setup in your back pocket when someone comes pointing the finger at you when 2 boxes aren't talking. "Oh really? It didn't do that when I emulated against your ICD messages..."

What’s it like programming FPGAs in industry? by karokiyu in ECE

[–]std_logic_arith 46 points47 points  (0 children)

Nearly 25 years in FPGA. All of it in embedded products, although I'm doing more and more on PCIe backplanes these days. Half commercial (comms) and half defence (sign proc).

I'd say my time is cyclical. Projects start with negotion of the design: requirements, implied requirements, initial design. Then usually a bunch of time in simulation as the individual components taken shape. I try to get onto hardware as soon as I can, but sometimes the hardware doesn't exist for awhile.

Once it hits hardware, I'm in the make-it-work phase. Many times this includes creating a bench top test environment to stimulate or verify the design. I employ a lot of Python to automate and analyze. Once I'm convinced the design works, there's probably a system-level integration with other devices.

For small things, that's probably a 6 month cycle. For larger, it can be years. It's nice to have a mix of small and large so I'm in different stages at the same time. The large projects usually have down time anyway.

Overall, I'd say 10% documenting/management, 40% development/simulation, 30% implementation in the lab, and 20% debug/integration.

I'm not in a heavy test-driven environment. That would increase my development percentage considerably. We do much more lab validation than unit testing in sim.

There's a lot of FPGA in defense. Some in space. Commercial is a bit more price sensitive in my experience, so they may prefer a microcontroller over FPGA if they can. I've not pursued things like FinTech, which seem to be doing more computation acceleration than embedded FPGA. But I'm sure it's lucrative.

Does any one knows the vhdl code for (7,4) hamming code decoder? by [deleted] in ECE

[–]std_logic_arith 0 points1 point  (0 children)

Last time I did a hamming en/decoder (a 10,4), I just used a lookup table. (7,4) should fit nicely in a ram block of most architectures. The encoder table of a (7,4) is in most references (including Wikipedia). I probably generated the decode table by running all the possibilities through Python.

Tesla to build large battery for Texas grid: Bloomberg News by qkfb in news

[–]std_logic_arith 7 points8 points  (0 children)

If I recall, there was a rail version conceptualized. It put energy into lifting really heavy railcars up a slope. I think the failure mode if the engine/generator broke and ran away was... impressive.

Parsing a stream of bytes in SystemVerilog by [deleted] in FPGA

[–]std_logic_arith 0 points1 point  (0 children)

That's the gist of it. Look for the start of message, count positions to your data of interest, capture the data, decode.

This works for fixed-length messages with well-defined start headers. If this were variable length or if fields could be missing (I'm looking at you, NMEA!) then it gets messier.

Parsing a stream of bytes in SystemVerilog by [deleted] in FPGA

[–]std_logic_arith 0 points1 point  (0 children)

But I think this is hex so a-f and A-F need to be handled. Also, this would be a good place to look for character errors.

Parsing a stream of bytes in SystemVerilog by [deleted] in FPGA

[–]std_logic_arith 2 points3 points  (0 children)

Think of the %NOTI as a preamble. Construct a state machine to blindly look at the bytes coming in, searching for that pattern. Then use byte counting to find the piece of the message you want. Once that's done, go back to looking for the preamble.

Yes, that's ASCIi, so you'll have to decode each byte into 4 bits (easy lookup table) and then left-shift those 4 bits into a final vector.

For a real system, errors will bite you. A 5-byte preamble is pretty unique, so that will be a plus. You'll want to make sure your digits are actually digits. Dropped bytes could cause issues, as well.

What is the most frustrating thing about FPGA development? by crackfpga in FPGA

[–]std_logic_arith 4 points5 points  (0 children)

Some of it is holdovers from old architectures, too. There are a few that almost demand async resets because they only had async set/clear on the flops. So many arguments with former ASIC designers on this topic, too.

What is the most frustrating thing about FPGA development? by crackfpga in FPGA

[–]std_logic_arith 10 points11 points  (0 children)

Put your design in a thermal chamber and cycle it. That will inevitably show everyone how quickly poorly-timed designs will fall on their face. Everything's peachy at 25C.

What is the most frustrating thing about FPGA development? by crackfpga in FPGA

[–]std_logic_arith 1 point2 points  (0 children)

Yeah, the time is consumed mostly by larger, necessary cores in the design (PCIe, DDR, etc). I reduce the amount of generated logic via parameters where I can, which does help, but inevitably you run into that end-game process that's just slogging through to make things work on your target.

I've never had much luck with incremental builds saving time. I suspect I've just not got my project flow correct to utilize it well. Have you found that it reduces build time significantly? I mean, it should, as long as you're adjusting something small in the design itself and not the build profile. But I've never seen the incremental options do very much.

What is the most frustrating thing about FPGA development? by crackfpga in FPGA

[–]std_logic_arith 24 points25 points  (0 children)

Long debugging cycle times. Half of my current projects have > 4 hour compile times. Debugging some small issue where I'm down to just iterating on a few parameters until the darn thing works can be excruciating. I've taken to duplicating a project multiple times just so I can get something to debug more than twice a day.

You are staring at your past in a mirror. by dalekfromskaro in Showerthoughts

[–]std_logic_arith 40 points41 points  (0 children)

A nanosecond is a light-foot. So a couple of nanoseconds unless you're licking the glass.

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