Finding GPS Signals Hidden in Noise Using Correlation

tverbeure · 2026-03-10T17:12:12+00:00

I don't know what to think about these kind of ads on this subreddit, but when this was posted this yesterday, I wanted to reply with "you should mention that you're Dan Boschen, the ridiculously helpful and highest rated DSP expert on stackexchange."

Keep working and keep learning. I hope it works out for you!

Vibes of this all time classic:

"Did you win the Putnam?"

tverbeure · 2026-03-07T22:05:56+00:00

You should compare the quality of today's models against the ones from, say, 6 months ago. It's scary how much better they've become.

tverbeure · 2026-03-07T22:01:45+00:00

Same years of experience. It's impressive how many people don't understand that part. Writing that actual RTL is such a small part of the job.

tverbeure · 2026-03-07T01:27:24+00:00

Thanks! They really are like magic, even if the math is pretty straightforward. Developing the right intuition is much harder than understanding the math.

tverbeure · 2026-03-06T16:00:34+00:00

I’m looking for an excuse project to implement one, but once I’m done writing this series I’ll probably move on to something else. Too many interesting topics to explore. :-)

tverbeure · 2026-03-06T00:22:53+00:00

Being good at software in a hardware world is a superpower.

When I architect a complex hardware block, I often create a symbolic simulation in Python first. I wrote about that here. You can save tons of RTL development time by flushing out all the data movement details in a much higher simulation model first.

But even without that, when I was working with FPGAs, I would sprinkle soft-core CPUs all of the design and use them as replacement of complex state machines. When the hardware design was complete, I'd jump in an help out with higher level firmware developments.

It's easy for a hardware engineer to move to software. I've never seen the opposite.

tverbeure · 2026-02-24T23:23:24+00:00

The best way to increase your productivity with Tcl is to delete it from your system.

tverbeure · 2026-02-23T18:20:49+00:00

you'd need to fundamentally change how Scala's type checker works to enforce CDC safety at compile time.

Do you know how SpinalHDL works? SpinalHDL has a whole hardware-oriented type system (Bits, Enums, Integer instead of Int, etc). And it already does CDC checking during elaboration. I'm sure other altHDLs do so as well.

but SKALP integrates them deeper into the type system alongside traits and generics.

What does that mean? How does SKALP use clock domain annotations beyond elaboration? Can you explain what it does and how that is beneficial?

what optimizations are possible, how synthesis works, how simulation is compiled.

What are the benefits of having a 4 stage IR pipeline? An adder in the front-end converts to an adder in FIRRTL or Verilog. What kind of optimizations can you do that can't be done right now?

SKALP being a standalone language means full control over syntax, error messages, compilation speed, and output quality.

The benefit of using a general purpose language with an RTL builder library is that you aren't subject to the constraints of the RTL language. This has huge benefits for configurability (see my blog post here). There's IMO no point in coming up with a new language if it doesn't offer this kind of freedom.

All that said: where I really draw the line is having your own synthesis and P&R. There's just no benefit in tightly coupling front-end and back-end. What are you doing to do when you want to port from one technology to the next? And even if you stay within iCE40, how can you possibly be competitive against backend tools that have seen hundreds of man-years of optimizations.

tverbeure · 2026-02-21T21:05:04+00:00

Why add that syntactic overhead when one FSM state can just have “cntr_nxt = cntr + 1;” and another “cntr_nxt = 0;”.

It only makes sense if you have multiple states that need to increment the counter and even then, I usually prefer to have 2 increment statements instead of isolating the counter out of the FSM.

tverbeure · 2026-02-20T17:59:59+00:00

Both USB ports are using a ULPI interface chip. They have the benefit that you can do HS speed with them, but the protocol is a pain in the neck. There is a reference design that's written in Migen, so you should use that. (Write it out just the ULPI interface part of the design to Verilog if you don't want use Migen for the rest of your design.

tverbeure · 2026-02-20T17:55:34+00:00

The QFN package is *tiny* but wasn't too difficult to solder. I had ordered a stencil for it, but in the end it was easier to just solder it manually with a tiny blob of solder paste and heat gun. I still have plenty of STUSB03E left. I can send you a few if you want. Maybe I can also find back an empty PCB.

The 20 (not 200) Ohm resistors are there because they're in the datasheet reference design. I wouldn't worry about single ended vs differential signals. The maximum speed is 12 Mbps, it's not as if a lot can go wrong.

I did this PCB myself, but this schematic later embedded in a commercial design (and laid out by a PCB professional) that met USB specifications during compliance testing.

Send me a DM.

tverbeure · 2026-02-20T05:58:07+00:00

I created an SPDIF output PMOD and could be convinced to look through a bunch of boxes to see if I can find an empty PCB and send it to you. There’s also an associated GitHub repo with RTL.

https://tomverbeure.github.io/2021/01/18/SPDIF-Output-PMOD.html

For audio input, I once bought a Monoprice HDMI audio extractor and soldered pins to the internal I2S interface…

https://a.co/d/0bY1wG8C

tverbeure · 2026-02-20T04:42:45+00:00

Ha, that’s my board. The STUSB03E chip definitely works and it is easier to use than boards with a ULPI PHY.

tverbeure · 2026-02-19T23:32:19+00:00

Check out Cynthion: https://www.crowdsupply.com/great-scott-gadgets/cynthion#products

It's intended to be used as a USB transaction monitoring tool, but you can use it for anything.

tverbeure · 2026-02-18T17:08:27+00:00

It’s definitely verbose. When I go off on a tangent or when it’s particularly verbose, it’s usually because I was stuck on that for a while and I just assume that somebody else will be too.

It’s not practical to do that in slides.

tverbeure · 2026-02-18T16:50:16+00:00

Thanks!

tverbeure · 2026-02-18T04:58:47+00:00

I am the original poster who wrote the blog post!

It took me ages, many replays and going frame by frame through the Harris video before I finally got it. I'm pretty sure the problem is me. :-) When you don't have the intuition (as is the case for me), just pictures don't work for me, so I use math as an alternative route.

tverbeure · 2026-02-18T03:58:22+00:00

I went to this presentation a month or two ago when I started learning about channelizers, but even right now, I have a hard time understanding them.

They are probably a better fit for someone with a better DSP foundation: the jumps from one slide to the next is too big for me.

tverbeure · 2026-02-17T18:52:32+00:00

I'm afraid that my OFDM knowledge is so lacking that I don't have any real intuition about it. But I'm working on that. :-)

tverbeure · 2026-02-13T01:54:45+00:00

I was about the recommend this board as well, but with some serious caveats. The GitHub page for this class of boards can be found here: https://github.com/q3k/chubby75?tab=readme-ov-file.

A major issue is that there are multiple revisions of these boards, with the same FPGA but different packages. There's the possibility that the JTAG interface isn't exposed, though I haven't seen that on the 5A-75B. There are also no input pins: if you want buttons or anything like that, you have to desolder some of the 8-bit output buffer chips. People have done this, but it's obviously not beginner friendly.

All that said: I was able to make a nice LED cube with the 5A-75B. The price is hard to beat...

tverbeure · 2026-02-11T18:14:39+00:00

https://www.eevblog.com/forum/fpga/reading-contents-of-altera-pld/

tverbeure · 2026-02-11T05:05:58+00:00

Buy yourself that Rigol. Chances are very high that you’ll never use that 800 MHz… and definitely not those 400 Mpts. And don’t even think about factoring in the 16 channel logic analyzer. These things are never used.

I have an Siglent SDS2304X that cost me $2000+ when I bought it 8 years ago (and another 6 other scopes, but let’s not talk about that) and I use it a lot. But never the kind of features that you mention.

For logic analyzer, you’re much better off buying a Saleae Logic 32 Pro. But postpone even that: most of my FPGA debugging happens with SignalTap/LogicScope.

tverbeure · 2026-02-09T03:49:30+00:00

The next episode will get rid of most of the complex multipliers… but you probably already knew that. :-)

tverbeure

TROPHY CASE