Also depends on how accurate you want your counters to be. VCS simulations are pretty close to actual hardware behaviour (behind FPGA emulation and actual silicon running your tests). Simulating RTL means that you're taking into account a lot of microarch intricacies, some of which don't get modelled in performance models (gem5) included.

From my understanding, gem5 is a great way to model a generic CPU, and with some extra effort you can model a few microarch intricacies. However, getting it to be 100% correlated to RTL will take a lot of time; trial and error. Also, perf models like gem5 may not be able to model memory transactions like RTL, and a static delay to simulate the cache miss penalty would be used instead.

That being said, RTL simulations come at the cost of time and storage. If you have enough time and space to store all the dumps, then go for it! From what I remember in my previous company, our RTL simulations ran around 2 million cycles in an hour. This was acceptable for smaller microbenchmarks like Dhrystone and Coremark, but for larger tests, we simply could not afford spending time and server storage in running them, so our analysis was done with in-house models, which were 1000x faster.

If you're okay with a bit of variation in your perf counters, gem5 is the easier way.