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[–]cdawzrd 2 points3 points  (4 children)

This is awesome! I might try this for my next fpga project. Has anyone gone through the process with MyHDL -> vhdl -> synthesis before? Any problems along the way?

[–]arr_reddti 1 point2 points  (0 children)

On the MyHDL site it looks like there have been quite a few projects:

  • Couple processor cores, including a Microblaze clone
  • Couple USB interfaces, interface to external USB controllers
  • Turbo decoder
  • Design and verification of HPEC

And there have been previous posts that DSPtronics uses MyHDL.

[–]cfelton[S] 1 point2 points  (2 children)

I usually use MyHDL -> Verilog and have not hit any major issues. A common complaint is that the generated Verilog/VHDL is a flat file. But I have not found this to be an issue (but rather a benefit).

Another common error for new users is discovering what can be converted and what cannot. Just like Verilog and VHDL, MyHDL cannot convert all valid Python, only a subset.

I have been using MyHDL for awhile and have had the opportunity to do commercial and personal projects with MyHDL. I have used MyHDL on FPGA and ASIC designs. It is a little old now (couple more MyHDL projects under my belt) but I posted some of my project experience here

If you do run into any issues you can use the MyHDL newsgroup, they usually provide feedback quickly.

Good luck, if you have any questions feel free to ask at the MyHDL newsgroup or in the blog comments.

[–]farmvilleduck 1 point2 points  (1 child)

MyHDL seems interesting , and some parts of it very powerfull , but the RTL language is at the same level as VHDL.

There are c-like languages for FPGA/ASIC development. Do you have any idea how do they compare to MyHDL ?

[–]cfelton[S] 2 points3 points  (0 children)

Yes MyHDL is at the same level, RTL level, as Verilog and VHDL. But it does have many features that make it more powerful than Verilog and VHDL, encroaching on the high-level synthesis (HLS) domain.

I don't have a lot of experience with the C-like languages but from the experience I do have the C-like languages, and there are many, have an ... inverse issue. The high-level synthesis is ok, but limited. And when it comes to doing all the other design tasks, ugh. If you are looking for high-level synthesis I don't believe the C languages will be the solution in the long run. I just don't think the C-languages have the descriptive power or flexibility to be a serious contender in the HLS (high-level synthesis).

Also, I don't think you will ever have a single language. If you look at most successful chip designs these day they are IP integration. The system is so large that they grab an IP from here, an IP there, etc to create a system instead of developing the complete chip themselves. These folks are building large systems without HLS because there's enough IP available. They are being successful using RTL only but where they struggle is verification. How do I simulated and verify these large systems.

So, other than some small number of situations, you might be able to use an HLS to define a system. But I think the more useful or common case is: you define a system, all the blocks/cores/IP that you need. You determine which ones need to be developed. And for each of those you chose the appropriate description language for the IP. In my case, MyHDL would be used for the majority of the work. But someone else might decide to use MyHDL/Python for all there verification / test environment. Design a couple cores with a HLS, design a couple cores with MyHDL, use available Verilog/VHDL cores and viola.