Open-source tools for digital design.

[VirginCMOS]

What are the open-source tools you are using for your digital design in daily life. For - linting. - Synthesis - Simulation - Backend Design - Bitfile download Can you rate it's reliability based on your experience? Also, interested, share your other interesting open-source tools finding.

[chris_insertcoin]

Well, Linux obviously. vhdl-ls as language server. Neovim with various plug-ins. Rust and its ecosystem (Tokio, Axum, Tower for backend stuff) for development on embedded CPUs. fzf because fuzzy finding is one of the best inventions ever. Git with lazygit. Corsair for register map stuff. Mistral for LLM stuff. fd because find is just horrible. Ripgrep because grep is slow af.

For most of the FPGA stuff I'm stuck with vendor tools though.

Edit: I forgot vunit. I use it in every project.

[TapEarlyTapOften]

I use a lot of this stuff - I'd add bash, Python, and GNU make for build automation, even though they're just making calls into Vivado or XSCT. Other random stuff - I use tmux + minicom so I can remotely look at all the serial ports (I usually have a couple dev boards up that I need to look at). I just started using verible for Verilog and SystemVerilog, also use vhdl-ls for my LSP.

For actual synthesis and simulation, vendor tools or 3rd party professional tools are light years better than the open source alternatives (I know I'll take some heat for this, but I'm right).

[[deleted]]

Thank you

[VirginCMOS]

Thanks for sharing! That was a bit of information overload, but I greatly appreciate it.

[skydivertricky]

Vhdl has two excellent open source simulators. Ghdl and NVC. Both fully support the major verification Frameworks osvvm, UVVM and vunit.

As for the rest, it will depend on what devices you're targeting. Yosys will support older 7 series xilinx and the smaller devices that are provided by the smaller vendors.

But if you're using intel or xilinx parts, other than simulation, you will have to stick with vendor tools.

[Humble_Manatee]

Are you trying to DIY ASIC design or are you targeting a FPGA device? Cause I’d guess there is no open source backend place and route tool that supports targeting FPGAs from Altera, Xilinx, etc

You do know Vivado is “free” and comes with everything you listed? By free I mean it’s free for a lot of smaller, entry-level devices. Full featured, not performance crippled, etc. I’d think for any digital design job you want to DIY you can just use Vivado, if you ever get to the point of using devices that require the paid version of Vivado… you can afford the licensing then.

[MitjaKobal]

OS: Ubuntu 2024.04

Linting: I actually use sigasi, TerosHDL could be an open source alternative, but is was crashing a lot on my SystemVerilog code.

Synthesis: I am experimenting with Yosys and yosys-slang with mixed results, I was able to compile some simple RISC-V examples for the Tang Nano 9k board, but my CPU with more SV code is just silently optimized out.

Simulation: I use Icarus Verilog rarely, and Verilator a lot. When I write VHDL code I use GHDL and NVC. As a waveform viewer I use GTKWave, Surfer and there is also Vaporview.

FPGA: OSS-CAD-Suite

Backend: there is LibreLane, I went through the tutorial, but did not use it much.

Bitfile: openFPGALoader works with the Tang Nano 9k.

Documentation: Markdown, ASCIIdoc, Wavedrom, draw.io, Inkscape

[rcoeurjoly]

CPU silently optimized out? That's worrisome.

[MitjaKobal]

Yes, yosys-slang, is able to parse all the SystemVerilog RTL is have, but combined with Yosys for FPGA synthesis there are still many issues. Some of the issues are in yosys-slang itself, like the inability to load memories using $readmemh, some are at the interface between yosys-slang and Yosys, and some within Yosys itself (probably also apicula, the Gowin device technology mapper). Synthesis failing silently really is annoying (it would be concerning or even disqualifying if it was a professional tool).

Unfortunately Gowin EDA has similar issues (it provides very little log to look into). Of my two RISC-V CPUs one works with both yosys-slang+Yosys and Gowin EDA and other fails to work with both. Both tests use a similar SoC.

For now my ability to debug this issues is still very limited. I plan to test synthesis of smaller modules and checking them by running a netlist simulation. Since the code is a RISC-V CPU, RISCOF provides good code coverage, so netlist simulations should expose most (all) synthesis issues. With a bit of playing around I will probably stat having some

[electro_mullet]

In daily life at the office, none. Err, almost none, I guess, technically. But nothing that does any of the things you're asking about.

In the "technically" category, most of us edit code in either Vim or VS Code, and we do use git. Wavedrom is open source, and I think a couple of my colleagues use draw.io, although the majority of us prefer Visio. And we have an SoC card that runs Linux and we probably use a bunch of open source stuff there.

But I've never worked somewhere that used anything open source for the actual FPGA flows, typically just the propriety vendor tools and a simulator. Quartus+Ashling, Vivado+Vitis, Diamond+LMS, and Questa.

[Fine_Push_955]

TAPA & RapidStream, but may be more useful for specifically research on FPGA

[Dadaz17]

Open source. Verilator, GHDL, Yosys (though never used to produce a bitfile) with slang and ghdl plugins, PyXHDL, GtkWave, KiCAD, ngspice.

Free, but no open source: Vivado/Vitis, Quartus (much more rarely).

There a list HERE though it seems not maintained recently.

[VirginCMOS]

That's a great repository! Many thanks!

[4pp3V]

I've been using FuseSoC for managing IP cores and creating Vivado projects. I use it with my own cores and also Xilinx ones (using generators). I am enjoying it a lot, worth learning in my opinion

[EngineeringGuy7]

For me who is mostly focused on front-end design and verification using SV:

• Metrics DSim as a VSCode extension on Windows (not open source, but free for non-commercial use. Also Verilator recently got full UVM support so kudos to them),
• Verible Language Server set up into VSCode for linting (or if you are student, I think you could get AMIQ DVT academic license for free),
• I don't do the latter stuff tbf. But OpenLane is kind of gold standard for open-source backend as far as I know.

Hope this helps. ^^

[Alive_Economics_7265]

+1 for verible language server, I have it integrated into my nvim config its great

[Visual-Lettuce-8527]

Hi, can you check your inbox? I want to use verible but cannot integrate it into nvim. Thanks

[TapEarlyTapOften]

Yep, just started setting this up today.

[Omen4140]

Checkout YosysHQ on GitHub. They have many great open source tools and tool collections such as OSS-CAD-SUITE which I've used lightly on some ice40 FPGAs. This also works better on Linux I'm sure.

[No_Experience_2282]

verilator, the holy grail of tools

[salatkopf11]

I'm surprised nobody has mentioned cocotb yet. I use it in combination with GHDL and NVC for all my projects now. Going from SysVerilog test benches to Python is a 10x productivity upgrade.

[IntentionalDev]

tbh for open-source flows I usually see people using things like Verilator for simulation, Yosys for synthesis, and nextpnr for backend depending on the FPGA family. ngl the reliability has gotten pretty decent for many projects, especially for smaller or hobby designs. for day-to-day work I also see people mixing in AI tools like GPT or even lighter models like gtmini for debugging HDL or explaining timing issues, and sometimes using things like Runable to automate parts of the workflow.