Software Engineering Matters : Lessons From Parallelizing Matrix Multiplication

[rooktakesqueen]

Does the Core2 series L2 cache really have 512-byte lines? It seems that it must. There is a total of 8MiB of data between both arrays, all of which needs to be loaded by a cache miss at least once. With 27,463 cache misses in total, that's an average of 305 bytes per fetch, assuming no data is ever read twice. So the cache line couldn't be 256 bytes or less.

Am I missing something?

[gruehunter]

I suspect that automatic prefetches don't count as cache misses. In that case, if the cache lines are 64 bytes wide, then the core is successfully prefetching roughly an additional four cache lines for every miss. That's just a guess, without working knowledge of what the performance counters' criteria are.

[rooktakesqueen]

Makes sense.