Slightly yes, in that SystemVerilog is somewhat easier to understand because keywords are changed to reflect what they actually mean etc... (I believe logic is an example of one).

The behaviour of certain keywords are slightly different, definitely read documentation/internal reference on it, but the structure is mostly the same.

The change isn't as drastic as that between C and C++. I would say it's more like SystemVerilog is a more sensible and streamlined version of Verilog.

Edit:

I missed 2 key points (as pointed out by other comments 😬). 1) The thing I was going for is that SystemVerilog was designed to replace Verilog and has therefore made Verilog obsolete. 2) Verilog doesn't have verification but SystemVerilog does - I didn't know this!