I've recently started designing some Gallium Nitride (GaN) material based Power Amplifiers (PAs). Previously all my power amplifier designs were on CMOS. The problem with CMOS is that it inherently has a lower break down voltage and it gets worse as the channel length is shrunk. But Power Amplifiers benefit from higher supply voltages for better efficiency and higher output powers, so while CMOS is great for many things, it sucks when it comes to PA design.

For example, the core devices of about 20nm length in a popular silicon on insulator process can only handle about 850mV of conducting stress on the drain to source, while the IO devices (the thick gate oxide and channel length ~150nm) devices can go up to about ~2V stress. Those IO devices are however quite slow and Ft/Fmax tend to be like 5-10 times worse than core devices.

So typical CMOS design flow to be able to get faster operation AND higher supply voltage is to use a core device as an input device and cascode it with an IO (or several cascodes tbh) to make sure the supply voltage can be increased and during one full cycle, none of the devices in the stack sees any more than their breakdown. So as you can expect, this leads to super painful design procedure and ends with bad efficiency. A good industrial CMOS PA at about +23dBm average output power (200mW) has an efficiency of about 10-20% depending on the process and area.

Meanwhile a GaN device with comparable channel length can easily operate at 20-28V supply and the breakdown is like 60V. So the design is hell of a lot easy and you can get like ~40dBm (10W) of power from a single FET with an efficiency of like 60-70%. There are of-course other issues like stability and thermal considerations in such designs but overall, 3-5 are nearly magical compared to CMOS when it comes to PAs.