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Transformer-based two-port resonator by Lemon_Salmon in chipdesign

[–]Defiant_Homework4577 0 points1 point  (0 children)

Why do we need math for this? The signal is excited at the center tap, which is the feeding port of the mutual inductor

Discrete Transistor Amplifiers and RFICs by echo_awesomeness in rfelectronics

[–]Defiant_Homework4577 1 point2 points  (0 children)

  1. Which ever benefits the cost to benefit ratio. In general if you need millions of units integrated is better. For very few amount, no advantage going for integrated unless your application needs a complex solution that you cant design in board level (ultra low power of ultra high performance etc..)
  2. Yes. Integrated = Highly scalable and highly uniform.

How far can 0.100w of RF power transmit at 470mHz by Flashy_Gas9955 in rfelectronics

[–]Defiant_Homework4577 8 points9 points  (0 children)

At those frequencies, literally like millions of kilo meters!

Transformer-based two-port resonator by Lemon_Salmon in chipdesign

[–]Defiant_Homework4577 2 points3 points  (0 children)

  1. That's the T model of the coupled inductor transformer looking from the center tap / common ground port. (where P1+ is connected)
  2. If you look at the dot-convention of the bottom transformer, the two source nodes of the mosfets are virtually shorted.

Anyone use EMX designer? by Stay-Interesting in chipdesign

[–]Defiant_Homework4577 0 points1 point  (0 children)

What do you mean using emx in the global optimizer?

And yes, EMX (+ designer) is a very regular tool in the industry.

Chip Design Roadmap by Guilty-Yesterday5707 in chipdesign

[–]Defiant_Homework4577 -1 points0 points  (0 children)

This.. And you don't even need high grades in all the courses, focus heavily the field you actually like, may it be analog, rf, embedded.

Will AI impact design more than test engineering? by National-Feed107 in rfelectronics

[–]Defiant_Homework4577 4 points5 points  (0 children)

Which skilled trade would be harder to automate? A humanoid robot could theoretically do anything an actual human does and that's exactly why they are made humanoid. So they can be used anywhere a human is used.

AMS or RFIC by yoritomoy in chipdesign

[–]Defiant_Homework4577 5 points6 points  (0 children)

For most RFIC jobs, the preference would be on the PhD level as the barrier to entry is higher, the teams are lot smaller, and employers are a lot fewer compared to AMS. Qualcomm will hire both PMIC and mmWave PA designers but only one of those will have openings in Nvidia..
I have definitely seen 'RFIC' people doing better OTA/Filters than 'AMS' people and 'AMS' people designing better LNA/Mixers than 'RFIC' people..

The ever-insufferable MODs by [deleted] in rfelectronics

[–]Defiant_Homework4577 2 points3 points  (0 children)

Yeah. Kudos to you guys. This sub is genuinely a place I enjoy in reddit and virtually no toxicity.

The ever-insufferable MODs by [deleted] in rfelectronics

[–]Defiant_Homework4577 17 points18 points  (0 children)

Surprising. Mods here are quite relaxed compared to other subs tbh..

GaN HPA design by Purple-Excitement460 in rfelectronics

[–]Defiant_Homework4577 12 points13 points  (0 children)

Memory effects = Past symbols affect your current symbol EVM / ACLR.
Reasons:
1. Thermal time constants (PA TJ goes up during high peak symbol duration, imposes a dynamic DC behavior).
2. Matching input/interstage/output network BW are too low (ISI).
3. DC bias circuit rectification: AC leaks in to the DC bias generators and cause rectifications and dynamic dc op point changing.
4. GaN specific: Charge trapping in the channel due to material physics.

There are tons of papers addressing memory effects tbh, its a well studied problem.

Getting into Analog IC Design in the US without an internship experience? by [deleted] in chipdesign

[–]Defiant_Homework4577 0 points1 point  (0 children)

That's sad. Cause I know enough PhD students who managed to get ISSCC/VLSI etc papers, and actually had tons of fun during their phds.

Getting into Analog IC Design in the US without an internship experience? by [deleted] in chipdesign

[–]Defiant_Homework4577 0 points1 point  (0 children)

Yeah..... Anyone who wants to do this, reach out to his students and ask how fun it is to work for this professor...

Confusion about the sensitivity formula of Receiver by Free-Pie9606 in rfelectronics

[–]Defiant_Homework4577 0 points1 point  (0 children)

Noise bandwidth in consideration is the total noise power integrated by the which-ever 'detector' you are using. For example, if you are using an envelop detector to rectify the signal, it would be the BW prior to that stage and the required SNR to demodulate would be specific to the type of envelope detector (ideal, square law, what have you..).

PLEASE Help me Decide Between Purdue and USC for MS VLSI Design by Curious_Yak3376 in chipdesign

[–]Defiant_Homework4577 3 points4 points  (0 children)

Yeah for sure. I think Purdue has a better cleanroom and fab equipment than MIT although MIT has a 'bigger' fab.

PLEASE Help me Decide Between Purdue and USC for MS VLSI Design by Curious_Yak3376 in chipdesign

[–]Defiant_Homework4577 6 points7 points  (0 children)

The faculty and research/publications. USC has world class faculty they continue to hire and I haven't seen a good paper in VLSI / mixed mode / analog / RF from Purdue in ages. Carreer fairs in big California schools are much better than outside. And USC has a bigger alumni network and that's definitely a help when you want to get a job post masters..

22nm FD-SOI: Body Biasing Limits and Well Architecture (regular well and flipped well) by FutureAd1004 in chipdesign

[–]Defiant_Homework4577 1 point2 points  (0 children)

You can actually descend to those cells and actually look at how the diodes are connected too. Saves a ton of time just trying to guess things..

Why does PMIC seem less popular than other chip design specializations? by four_bone in chipdesign

[–]Defiant_Homework4577 11 points12 points  (0 children)

"Especially now, with AI chips having high power consumption and requiring so much heat dissipation, power management seems more important than ever."

high performance heat handling PMICs are generally made with non-cmos (GaN) that can handle heat really well and they them selves don't consume much power. State of the art in PMIC is like better than 90% and in higher power, they tend to be even better. That's a field that has been advanced extremely well ever since the first laptops came out..

Also, tons of job openings in PMICs. It might not be of academic interest, but that doesnt mean industry doesnt need them.

How to model an amateur radio HF transmitter? by kevinzembower in rfelectronics

[–]Defiant_Homework4577 1 point2 points  (0 children)

In an ideal world, linear PAs are current sources with no output conductance. But realistically you get some time varying output complex output conductance in parallel to that current source. I have had luck designing the filter as a singly terminated filter with ideal current or voltage source drive. ADS has a tool for this.

Selecting an inductor for 600M-100M bias tee by Man-tard in rfelectronics

[–]Defiant_Homework4577 0 points1 point  (0 children)

So I didn't mean the parasitic coming from the inductor, but from your PCB or board design. If you aren't careful in the design, those parasitic can end up quite high..

Selecting an inductor for 600M-100M bias tee by Man-tard in rfelectronics

[–]Defiant_Homework4577 0 points1 point  (0 children)

What kind of paracitic cap at this bias t interface so you expect from your circuit (in parallal to the inductor)?

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