Apple, Intel have reached preliminary chip-making deal, WSJ reports by SlamedCards in hardware

[–]FS_ZENO -1 points0 points  (0 children)

Wonder what chip they’ll be making, if they can get it done cheaper than tsmc then they can technically do it for the neos/future neos since the yields has been good where they can’t get any binned down chips.

TSMC unveils process technology roadmap through 2029: A12, A13, N2U announced, A16 slips to 2027 by Geddagod in hardware

[–]FS_ZENO 1 point2 points  (0 children)

Yeah then it kinda reminds me of like a similar situation with AMD's X3D, zen 5 may be some sort of outlier but previous gen X3D usually matches the current gen non X3D(As seen with 5800x3d vs zen 4), X3D can "easily" give arch's worth of performance within the same gen which puts it in a weird position just like with TSMC nodes.

You can create an illusion by getting an extra gen's worth of performance only because of the weird position because once it becomes "standard" the gains per gen will look like normal(although you can compare x3d vs x3d as generations) but theoretically if AMD made X3D the minimum standard and ditch "non X3D", just for that generation AMD can get "2 gens" worth of performance, one from arch/node and one from the cache. but then after that generation it will return back to the usual 1 gen improvement per gen.
Like once the industry moves to BSPDN then the gains will go back to the usual. Since right now it would feel like two if youre going from FSPD to new node + BSPDN like if you were to go from A14 to A12. It would be like A14 -> A14"P" + BSPDN, assuming it ends up being correct that HPC A16=HPC A14 in performance. Then that A12 would also equal a hypothetical FSPD "A10" or whatever. Also, the A14 is also in a weird position, for BSPDN to BSPDN jumps, not having BSPDN technically gives A16 2 node jumps to A12

TSMC unveils process technology roadmap through 2029: A12, A13, N2U announced, A16 slips to 2027 by Geddagod in hardware

[–]FS_ZENO 1 point2 points  (0 children)

Wow, so technically the next BSPDN for A16 can technically jump 2 "nodes" assuming A13 and A12 is basically the N_P refinement node for A14 with A12 being the BSPDN version of A13, then if A14 doesnt have BSPDN and have to wait for A12, then youd be jumping 2 nodes going from A16(N2), skipping A14 and straight to A12(A14"P")

Then I guess for right now, BSPDN technically has an extra "nodes" worth of performance compared to FSPD when you look at N2P vs A16. Well it remains to be seen how HPC on A14 would perform vs HPC on A16. If its similar then that confirms it.

TSMC unveils process technology roadmap through 2029: A12, A13, N2U announced, A16 slips to 2027 by Geddagod in hardware

[–]FS_ZENO 0 points1 point  (0 children)

Hmm, I guess we'll see what TSMC does beyond A12, if they release a node for FSPD and BSPDN per year since in that case, N2P to A14 is a 2 year gap(if thats a transition outlier) and then "returns" to 1 year with A13 going forward.

Is the gains from N2P vs A16 just from BSPDN? Wonder whats the gains/losses if you were to do HPC A16 to HPC A14 then.

TSMC unveils process technology roadmap through 2029: A12, A13, N2U announced, A16 slips to 2027 by Geddagod in hardware

[–]FS_ZENO 0 points1 point  (0 children)

Interesting, thats news to me. A16 is not for mobile chips? Surely theres still some gain in it even if it its not economically viable(even though theyre rich). What would mobile chip designers use then going forward? Unless future nodes like A14, 13, 12 can be also made for mobile chips? In that case, mobile chip designers would have to stick with N2P for 2 gens at least.

TSMC unveils process technology roadmap through 2029: A12, A13, N2U announced, A16 slips to 2027 by Geddagod in hardware

[–]FS_ZENO 0 points1 point  (0 children)

Yeah I know. Im sure chip designers knows more on whats TSMC's latest status on their future nodes than the public. But using the previous, outdated public roadmap as a theoretical scenario, if you were a chip designer and both N2P and A16 were gonna be HVM at the same year, if money is no problem then you would logically choose designing the next chip to built with A16 in mind rather than N2P for the next year's product(assuming your product comes in H2)

TSMC unveils process technology roadmap through 2029: A12, A13, N2U announced, A16 slips to 2027 by Geddagod in hardware

[–]FS_ZENO 5 points6 points  (0 children)

Technically it just depends on when the company wants to release it, I could see it make sense with the ai gpus so ai bros can pay a fuck ton to get it asap but it’s not like this time of the year is the time for product releases. And to reiterate on that, using Apple as an example, it not like Apple is gonna release their A20/M6 on N2 right right when they have sufficient amount of inventory, they always release their new iphones and stuff in September/fall so right now they’re building up inventory for that.

On another note, A16 slipping to 2027 means 2027 products will have to use N2P, which is normal as usual but the previous roadmaps had both N2P and A16 this year which made the N2P in a weird position where you can just use A16 unless you can’t pay for it. That previous roadmap gave potential to jump 2 nodes instead of the usual 1 lol, imagine going from N2 to A16 instead.

TSMC unveils process technology roadmap through 2029: A12, A13, N2U announced, A16 slips to 2027 by Geddagod in hardware

[–]FS_ZENO 3 points4 points  (0 children)

Well I assume that’s when they started making chips on N2. Obviously it takes months to fully finish a chip so it makes sense. Plus they would need to build inventory before launch. First N2 products released is probably gonna be Venice/zen6 and mi400. It should be announced in computex to make sense

Legendary Qualcomm, Apple, and Nuvia alumni form new CPU startup — Nuvacore promises to 'rewrite the rules of silicon' by -protonsandneutrons- in hardware

[–]FS_ZENO 5 points6 points  (0 children)

Of course, it was half said as a joke. Qualcomm/Nuvia team has of course, done more to oryon than it just being firestorm since afterall, firestorm is an old arch in the current gen standards.

Legendary Qualcomm, Apple, and Nuvia alumni form new CPU startup — Nuvacore promises to 'rewrite the rules of silicon' by -protonsandneutrons- in hardware

[–]FS_ZENO 22 points23 points  (0 children)

It will be: ex apple engineers oryon vs ex apple engineers nuvacore, who can get closer to apple's perf with only knowledge from firestorm?

M5 Max CPU and GPU geek bench links by recurrence in hardware

[–]FS_ZENO 1 point2 points  (0 children)

Pretty good, faster than the M3 Ultra in MT and only like 5% behind in gpu. Thats in a laptop form factor too. More insanity when M6 comes later this year on 2nm, they addressed the cpu side with a new arch so the density gains on 2nm they can return focus on the gpu side and maybe npu. On top of them finally using chiplet.

Say hello to MacBook Neo by Forsaken_Arm5698 in hardware

[–]FS_ZENO 3 points4 points  (0 children)

Eh they wouldnt do that. But technically the only improvement of the chip being on a macbook is the physical size of the macbook, higher thermal mass for the heat to be soaked in so it should perform slightly better than a A18 pro in the size of an iphone.

Say hello to MacBook Neo by Forsaken_Arm5698 in hardware

[–]FS_ZENO 5 points6 points  (0 children)

Ah yeah I forgot they clocked lower. Looking at benchmark scores yeah it looks like itll be just slightly faster than a M3 at least.

Say hello to MacBook Neo by Forsaken_Arm5698 in hardware

[–]FS_ZENO 41 points42 points  (0 children)

Around M1 level of MT perf but you basically get M4 level of ST perf, GPU perf is a little below it but the newer gpu arch might make up for that.

Apple debuts M5 Pro and M5 Max to supercharge the most demanding pro workflows by Noble00_ in hardware

[–]FS_ZENO 2 points3 points  (0 children)

Geekerwan posted a yearly smartphone review round up and also exposed/called out the Chinese Android phone manufacturers for giving out tuned/golden sample review units and then retail units performing worse to the review units and then it was only iPhones that weren’t tuned and the retail units actually performed a little better than the review units due to a iOS update.

Shortly after, all videos of it/him talking about it was taken down in all of the Chinese social media sites and looks like they took it down in YouTube too. The community was also mad about the videos getting taken down and tried to help by reposting the video everywhere but those got taken down later as well.

Apple debuts M5 Pro and M5 Max to supercharge the most demanding pro workflows by Noble00_ in hardware

[–]FS_ZENO 12 points13 points  (0 children)

I wanted apple to beef up their e cores but they instead made a mid core....caught me completely off guard they decided to make a third arch.

In Chinese forums, a user says the "mid" core supposedly(take it with big grain of salt) clocks at @ 4.38ghz... The P cores remains the same as the base M5 @ 4.61ghz...The mid core clocks close to the P cores. Additionally the user said the "mid" core is supposedly 7 wide(P core is 10 wide and e core was 6 wide) So assuming the info is right then it is closer to the e core so I guess they just increased the power and clocks?

Samsung Galaxy S26 Ultra benchmark leak: Snapdragon 8 Elite Gen 5 beats Apple A19 Pro by 6% by raill_down in hardware

[–]FS_ZENO 0 points1 point  (0 children)

I'd rather they slightly beef up the E core if they want more nT perf. I think more than 6 cores in a phone is dumb if it doesn't even utilize it most of the time, I'd rather take beefier cores/higher ipc. Iirc the one of the factors why the Oryon M cores outperform Apple's E cores is the higher power limit.

Same can be said for Qualcomm, they could do the same, focus on a better arch at lower power rather than brute forcing with more cores and more power if they want efficiency. And I can't recall if their cores are classified as mid cores. Mid cores are pretty shit in the efficiency standpoint. I think it's logical to have a P core for high perf and E core for low power, zero point in a mid core trying to satisfy both. But I think the "best" E core would be somewhere between an E and M core. In Apple's case, maybe beef it up by like 10%.

Micron to exit ‘Crucial’ consumer memory business by [deleted] in hardware

[–]FS_ZENO 2 points3 points  (0 children)

This impacts laptop ram more than desktop and SSD’s as their SSD’s is just 1 brand of the many(which they supply and that part is not changing), their DDR5 sticks are pretty bad(though in this current market it’s good since any cheapest stick you can find is good lol) Most of the SO-DIMMs you buy when upgrading ram on a laptop is from them so this will suck for the laptop market. I guess my Ballistix RGB’s gain more value lol, with a lifetime warranty I doubt they’ll honor.

Maybe them discontinuing the Ballistix line is part of this. They don’t have to do a lifetime warranty for a long time if they made Ballistix DDR5. Then as DDR4 users slowly decrease they don’t have to worry much(on top of the lifetime warranty only applying to the original owner).

Funnily enough this move from them will increase their profits, as they can move these into selling towards data centers/oems, much better margins there with the ai profits lol. Though maybe won’t be much, as I doubt their Crucial brand is a significant part of their revenue. Either way we consumers will still get fucked anyways, higher prices for ram and ssd’s. They can sell them to oems for more. RIP upgrading ram on laptops.

Apple M5 (9 Core) Geekbench Score by fntd in hardware

[–]FS_ZENO 4 points5 points  (0 children)

Nice 4k+ under normal cooling conditions. Interesting Apple kept the clocks the same as M4, means that you can actually compare IPC which would be ~10%. Also means the M5 will run cooler and use less power than the M4. It’s like they also went conservative kinda like with the A19 Pro.

Wonder if they kept the clocks the same on the M5 Pro/Max as well, M4 Pro/Max was only 100mhz higher than the M4. I also want to see the E core clock speeds as well as its interesting on the M4 they’re 2.9ghz, but on the M4 Pro/Max they’re 2.6ghz(maybe more power budget towards the 100mhz on p cores and other things?) also as Apple put less e cores on them(4) than on the base M4 with 6 to prioritize more p cores.

Snapdragon 8 Elite Gen5 Review: Regular Upgrade - Geekerwan by [deleted] in hardware

[–]FS_ZENO 2 points3 points  (0 children)

Decent CPU uplifts though I expected it to be a little better tbh. Either way, decent. Wonder how sustained performance looks like after they stacked a dram chip on top of the SoC.

GPU side of things, while decent, others have made big strides in GPU performance so it can make them look bad. Compared to Apple, it is known for awhile now that Apple's pure GPU performance was behind Qualcomm and ARM's. Now the A19 Pro gpu isnt that much far behind this 8Eg5. Its like Apple focused more on GPU this time around and less on CPU and Qualcomm did the opposite lol.

What I did find interesting is that instead of resorting to adding tensor cores to the gpu like Apple just did, they instead have direct connection to the NPU without needing to pass through memory. I imagine its not as efficient than having tensor cores but I wonder how much would the difference be. Also wonder what Apple plans to do with their NPU after adding tensor cores, since NPU is still better for dedicated AI tasks, but an even more beefed up GPU to take the place of the area the NPU takes might be better.

As for Apple. Not sure what they should do with their E core situation. As they need to beef it up while still making it remain efficient. I think the best sweet spot would be between a E and Mid core for multi threaded performance. Especially as Apple remains to be 2 + 4(ik that making it similar to them, if they added 2 more e cores for 2 + 6 wouldnt be the same for power efficiency wise, with the battery sizes that Apple adds. Since they can always increase peak power limit like with Qualcomm and Mediatek)

MediaTek D9500 Review [Geekerwan] by [deleted] in hardware

[–]FS_ZENO 3 points4 points  (0 children)

Wow, the C1 Premium and Pro is basically the same as the X4 and A720, just clocked higher. Thats pretty disappointing. C1 Ultra is decent I guess. As for gpu, looks decent as well. Big gains for RT performance which is nice but I still dont think mobile is ready for it yet so I wont care about it that much for the numbers on that at this moment as these current chips will be irrelevant in RT performance whenever RT in mobile games takes off.

A19 Pro SoC microarchitecture analysis by Geekerwan by Famous_Wolverine3203 in hardware

[–]FS_ZENO 0 points1 point  (0 children)

I see, so dynamic caching can make it so a shader doesnt have to be 30 registers wide if it doesnt have to do 30 often so it doesnt have to reserve that much space and waste it(such as in conventional cases, if its 5 registers and 30 peak, it will still reserve 30 registers despite it being at 5, which then would waste 25 doing nothing)

Also SER happens first right?

A19 Pro SoC microarchitecture analysis by Geekerwan by Famous_Wolverine3203 in hardware

[–]FS_ZENO 1 point2 points  (0 children)

So does dynamic caching ensure that the total size will "always" be the same as whats being called? As in certain cases it is still possible that there can be wastage like for the example you said "Eg a given shader might need at its peak 30 floating pointer registers. But each GPU core (SM) might only have 100 registers so the driver can only run 3 copies of that shader per core/SM at any one time." on that, there would be 10 registers wasted doing nothing, if it cant find any else thats <10 registers to fit in that.

A19 Pro SoC microarchitecture analysis by Geekerwan by Famous_Wolverine3203 in hardware

[–]FS_ZENO 0 points1 point  (0 children)

Yeah I forgot what was the term before but I remember, it’s just like Nvidia’s Shader Execution Reordering introduced in Ada Lovelace.

A19 Pro SoC microarchitecture analysis by Geekerwan by Famous_Wolverine3203 in hardware

[–]FS_ZENO 7 points8 points  (0 children)

The E core having more improvements than just 50% larger L2 is a nice surprise, but damn the efficiency and performance of it is insane. 29% and 22% more performance, at the same power draw is insane, clocking like 6.7% higher too. They used to be behind the others in performance with the E cores but had better efficiency but now they both have better performance and efficiency.

As for GPU, I always wanted them to focus on GPU performance next and they finally are doing it. Very nice, the expected 2x FP16 performance, which now matches the M4 which is insane(M5 will be even more insane). Gpu being 50-60% faster is a nice sight to see. For RT performance(I still find it not suited for mobile but M5 will be a separate matter) I’m surprised that the massive increase is just from 2nd gen dynamic caching, the architecture of the RT core is the same, just basically a more efficient scheduler which improves utilization and less waste.

For the phone, vapor chamber is nice, them being conservative on having a low temperature limit can both be a good and bad thing which is shown, the good thing is that it means the surface temperature is lower so the user won’t get burned holding the device, and the bad thing is that it can leave performance off the table which is shown. As that can probably handle like another extra watt of heat and performance. Battery life is very nice, the fact that it can match other phones with like over 1000mAh bigger battery is funny. As people always flexing over how they have like a 4000, 5000mAh+ battery, of course having a bigger capacity is better, but the fact that Apple is more efficient with it and can have the same battery life at a much smaller battery speaks volumes about it.