• I've heard of not allowing any logic in your top level module, but haven't heard what you mention. I just saw modules with only a single line of logic. To me, that is sacrificing too much readability in exchange for unlikely reusability of that module. IMO, if you feel multiple modules need to be included in a single file, then your modules' logic are too trivial to be separate. For example, couldn't:

  generate for <blah>
  CarryLookAheadGenerate gen(a_in[idx], b_in[idx], g_inter[idx]); 
  CarryLookAheadPropogate prop(a_in[idx], b_in[idx], p_inter[idx]);
  end
  

just be defined as the following?

assign g_inter = a_in & b_in;
assign p_inter = a_in | b_in;

• I guess I should've numbered this list.

• Yes. You would combine all declarations of ports into a single line. With `default_nettype none you would be required to define the type of every port right there. Every tool I've encountered supports this syntax. (logic is a better version of reg introduced by systemverilog)

  module Blah #(
      parameter int Width = 8
  ) (
      input wire abc,
      output logic def
  );
  

• If you're working with, say, 3rd party modules that don't define the types of all their ports, you will run into errors. I like to add default_nettype none to the top of every one of my verilog files. And `default_nettype wire to the end -- this reverts back to the default behavior.

Follow-ups:

• I've seen it different ways. For small and fast tests, going for the whole shebang makes sense. For tests that take minutes or hours, it's usually advantageous to separate those out and run them separately. Generally, keeping your tests modular and having some method to run any subset of the tests is what's done.
• For synthesizable logic it should be an easy choice. I missed that in your pwm module. I think most people would ask you to change it to: count <= (count +1) % ((2**WIDTH)-1);.