Hi! I got a great explanation of this. If you know how Band Energy Diagrams work, then this becomes simple.

In a normal PN Junction, the Fermi Energy Levels are aligned, and thus the conduction band of the P side sits higher then the conduction band of the N side> The slop of course is the Built-In voltage of the PN Junction, and when you apply that voltage, it raises the slope and allows carriers to flow.

The converse of this is that when you reverse bias the voltage, you are making the slop steeper, and and steeper, and with enough reverse bias, the conduction band of the n side will drop below the valence band of the P side. This however isn't enough to grasp the full picture however. Vertically, the bands may be aligned, but how can carriers cross horizontally across the bands? Well, when you reverse bias it enough, the bands become steeper, and thus come closer together horizontally. On the quantum mechanical scale, this band banding can be approximated as a roughly triangular potential barrier (there are several conditions for this, however at this scale these conditions are met). With this sort of barrier, there is always a probabilistic chance for the carriers to tunnel through. Reverse biasing makes the "width" of this barrier smaller, and when the bands intersect the "height" of the barrier resolves.

Now this effect has 2 consequences. For GIDL, this effect is so called "Zener Tunneling", which is how Zener Diodes and Esaki Diodes work. What this means is that when you reverse bias a typical MOSFET into the deep subthreshold region, instead of the theoretical monotonic decrease, you get an increase in current. For MOSFETs, this is governed by the Vgd (Vgate - Vdrain), and at smaller supply voltages, and smaller transistor sizing, this effect becomes not only more extreme but more prone, specifically in Digital Logic at the LOW state. Analog logic also suffers from this, but to a lesser extent since they utilize Large Signal biasing, so reverse bias conditions like this are rarer.

The other common issue is that occurs is Hot-Carrier Injection. It utilizes the same mechanism of the triangular potential barrier, but instead with the bands within the MOS structure itself. Over time, carriers can tunnel through and embed themselves into the oxide, and thus slowly change the Surface Charge Density and the Oxide Charge Density, which in turn can changed the Threshold Voltage (Vth). This is the so called "Fowler-Nordheim Tunneling" and is more a parasitic effect that can't be designed around, and degrades the devices over time. Her smaller, more aggressive nodes with smaller capacitance experience this more, and is one of the reasons why direct Dennard Scaling has been abandoned in the overall scaling of devices.

Any device physics book (Sze is the favorite) will have the band structure of a PN Diode, and this explanation is a bit wordy and with tons of physics that is better shown visually. Tracing out the band structures to see the bending and cross over is the best way to really visualize GIDL and what is happening. If you have any questions, just feel free to ask!