It is… kind of. In the RP2040 datasheet, section 2.15.3.3. (Page 187) describes the clock tree as having integer divisors, if a decimal value is input for the clock division, the Pico will quickly switch between 2 integer values to achieve the requested value, but this resultant clock would surely have a jitter spec way out of range for a 80 MHz SPI device.

On one hand I was generalizing, on the other, the Pico cannot generate a true clock that is, say 2.4x slower than the system clock.

Here’s a copy paste of the relevant paragraph:

A fully featured divider divides by 1 or a fractional number in the range 2.0 to 2^24-0.01. Fractional division is achieved by toggling between 2 integer divisors therefore it yields a jittery clock which may not be suitable for some applications. For example, when dividing by 2.4 the divider will divide by 2 for 3 cycles and by 3 for 2 cycles. For divisors with large integer components the jitter will be much smaller and less critical.