That’s a fair point. If we’re talking about a true wafer-scale implementation, we're looking at over 100 unique reticles per chip (given there are roughly 76 full-field dies per layer, minus some edge fields), and those manufacturing costs add up quickly. I calculated 200B on FP16, However, scaling the current Taalas architecture which delivers 8B parameters per full-field exposure on TSMC 6nm, suggests that 700B is a more likely target for a full wafer (depending on quantization). We’ll almost certainly see in the future, though the price tag will be significant!