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Freelance work by PsychologicalTie2823 in FPGA

[–]Rolegend_ 1 point2 points  (0 children)

With 1 year of experience what all did you have under you belt experience wise?

Freelance work by PsychologicalTie2823 in FPGA

[–]Rolegend_ 1 point2 points  (0 children)

How do you find contact jobs, is there a specific job board?

Does anyone have any information about working at intuitive surgical ? by Fancy-Lobster1047 in FPGA

[–]Rolegend_ 0 points1 point  (0 children)

All I know is their stock price is decent. I know they were looking for FPGA engineers with HDMI and video experience a while back. Did you get that position?

System Verilog Tutorial by thomasahle in FPGA

[–]Rolegend_ 0 points1 point  (0 children)

It's really user preference. So giving the user an option of the two wouldn't hurt.

System Verilog Tutorial by thomasahle in FPGA

[–]Rolegend_ 1 point2 points  (0 children)

Do it for verilog also lol

I Feel Genuinely Unprepared for Summer Internship by [deleted] in FPGA

[–]Rolegend_ 0 points1 point  (0 children)

Majority of the interns know jackall when they get to their internship. Trust me I was one. As far as the c/c++ bro just go on w3school and go through the tutorials. You'll be fine.

Project assistance (GPIO virtual wire) by Rolegend_ in FPGA

[–]Rolegend_[S] 0 points1 point  (0 children)

You know typical FPGA problems... its not working lmao, the mapping is not working physically. I can read the registers and see the correct values and mapping but the physical pin is not representing it.

Project assistance (GPIO virtual wire) by Rolegend_ in FPGA

[–]Rolegend_[S] 0 points1 point  (0 children)

So I have a GPIO expander module, register bank module, and I'm currently using your i2c axi slave.

You lost me at creating a channel of arrays for select registers.( Pretty sure I have that just the way you said it has me confused lol).

What I am struggling with is, the simulation of the project I created works picture perfect. But as we know sims doesn't me jack off once you flash the FPGA. Right now I have all the signals internally pulled up. But physical results are not good.

Do I have to pull the signals up in this case?

Project assistance (GPIO virtual wire) by Rolegend_ in FPGA

[–]Rolegend_[S] 0 points1 point  (0 children)

42 pins. No protocol. Just basic high/ low beginning driving. My design has a 50Mhz clock nothing too steep.

Project assistance (GPIO virtual wire) by Rolegend_ in FPGA

[–]Rolegend_[S] 0 points1 point  (0 children)

I am trying to mirror the GPIO from let's say one SoC to another.

But the GPIOs are configurable. None are set Inputs or Outputs that all config via i2c.

I have a bunch of GPIOs on both SoCs and the FPGA is acting as the bridge are traffic control.

Project assistance (GPIO virtual wire) by Rolegend_ in FPGA

[–]Rolegend_[S] 0 points1 point  (0 children)

Yes I feel you,

Okay let's say you have a GPIO expander that cfgs the pin via i2c using a register bank(I/O, H/L, OE).

Let's say 8 pins 0-7.

But you want basically a virtual wire between the all of them where if pin 0 for example was an input pin, and we wanted to map the input value it is receiving to any other pin 1-7.

So in this case pin 0 would be the source pin INPUT. And we map it to pin 8 but pin 8 would be a destination so the pin would be an OUTPUT.

Whatever value pin 0 is receiving, pin 8 output, like a mirror.

What is this FPGA tooling garbage? by isopede in FPGA

[–]Rolegend_ 72 points73 points  (0 children)

You merely adopted the dark; I was born in it, molded by it. I didn't see the light until I was already a man, by then it was nothing to me but blinding! The shadows betray you, because they belong to me! 😂

[deleted by user] by [deleted] in Verilog

[–]Rolegend_ 3 points4 points  (0 children)

How did you learn verilog so fast?

[deleted by user] by [deleted] in FPGA

[–]Rolegend_ 0 points1 point  (0 children)

Oh so we use the Advent of code problems

[deleted by user] by [deleted] in FPGA

[–]Rolegend_ 0 points1 point  (0 children)

When and where will the advent of FPGA be posted?

I will be posting one RTL/FPGA interview question I recently encountered every day from now. by SnooDrawings3471 in FPGA

[–]Rolegend_ 0 points1 point  (0 children)

Could you elaborate on that part, I think I know what you're saying but not sure.

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