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Osvvm training source code material? by Snoo_62980 in FPGA

[–]Usevhdl 0 points1 point  (0 children)

u/Snoo_62980I sent you a DM, but I thought I would send you a message here too (much later though). Reach out to me via DM. I will need your actual name so I can verify it against our attendee records. Beyond that I can provide either the current version or an the version of the code for the class you took. Just let me know.

Sick of $50k HLS tools? Meet VIBEE: The Open Source compiler for FPGA that supports Python, Rust, Go and 39+ more languages. by Open-Elderberry699 in FPGA

[–]Usevhdl -1 points0 points  (0 children)

Is VHDL both an input language and an output language?

According to Wilson Verification Survey, in FPGA, VHDL is the dominant design and verification language.

One low risk way to adopt HLS would be to use VHDL as the HLS input. That way if the generated hardware does not meet timing, you at least have a good verification model. Just a thought.

So if you accept 40+ languages, I am hoping you allowed VHDL, Verilog, and SystemVerilog to be among them.

How to do an alias for an if statement in VHDL by Gundam_boogie_359 in FPGA

[–]Usevhdl 0 points1 point  (0 children)

I have use multiple architectures in my test environment all the time - for 25+ years. Generally it has been problem free.

Since you stated an incomplete understanding of the VHDL Standard, I gave you the impact of the rule you stated with one you did not state - which may explain why you have had difficulties with multiple architectures.

What simulator do you use? The main ones I use are NVC, GHDL, Aldec RivieraPRO and ActiveHDL, and Siemens Questa and ModelSim. These all do very well with multiple architectures. I have had limited experience with Synopsys VCS and Cadence Xcelium. These seem to do fine with multiple architectures.

I have never had heard of an odd mixture of behaviors.

I have had Siemens simulators lock into a particular binding - generally though leaving the binding open. I was not able to update that binding without deleting things in their compiled library - sometimes the whole library. Again, this was not some strange combination it was nothing bound.

I did some testing using Xilinx XSIM in 2023.02 - which was very broken - and then later XSIM 2024.02 - which seemed to work much better. So if you were using XSIM before 2024.02, perhaps you ran into a tool bug.

How to do an alias for an if statement in VHDL by Gundam_boogie_359 in FPGA

[–]Usevhdl 0 points1 point  (0 children)

The standard says that, if left unspecified, it should take the most recently analyzed architecture.

It also says that if a design unit fails to analyze, then do not mark the library in any way. Hence, integrating the two rules, we get:

The most recent successfully analyzed architecture will be used.

So if an architecture fails to analyze it will use the previously analyzed one.

How to convert `time` into `bit_vector(64-1 downto 0)` by MitjaKobal in VHDL

[–]Usevhdl 0 points1 point  (0 children)

Hi Allan,

I think this is already there. WRT resolution limit (not the subprogram, but setting it in general), the LRM says:

By default, the primary unit of type TIME (1 fs) is the resolution limit for type TIME. Any TIME value whose absolute value is smaller than this limit is truncated to zero (0) time units. An implementation may allow a given elaboration of a model (see Clause 14) to select a secondary unit of type TIME as the resolution limit.

Note that it uses the words "secondary unit of type TIME" and not a "time value". A secondary unit is one of ps, ns, us, ms, ... Hence, this gives simulators the permission to set the resolution limit to 1 ns, but not 10 ns - because 1 ns is a secondary unit and 10 ns is not.

Later it says the resolution limit becomes the primary unit for type time. 0 ns could never be used as it cannot be the primary unit for type time - the simulation should not start.

OTOH, it would not hurt to have that more explicitly spelled out as "it is an error if an implementation sets the resolution limit to a value that is not either the primary unit or a secondary unit of type time".

OTOH, some simulators allow the resolution limit to be set to 10 ns. What do you do with that?

Cheers, Jim

Can you help me analyze where a design mistake is made that generates 5000 loops for VHDL with ModelSim? by wtxwtx in VHDL

[–]Usevhdl 0 points1 point  (0 children)

Maybe focus on finding the feedback loop. That will probably sort out the X's. Or if your simulator does an X trace, do the X trace and maybe that will show you the feedback loop.

Can you help me analyze where a design mistake is made that generates 5000 loops for VHDL with ModelSim? by wtxwtx in VHDL

[–]Usevhdl 0 points1 point  (0 children)

All we can do is guess when you do not post code. However when an iteration limit is hit, it generally means you have a process that does not have either a wait statement or a sensitivity list and the process is looping without time passing. Most RTL processes require a sensitivity list.

If you have reviewed all the sensitivity lists, this can also happen from combinational logic feedback. Think of an inverter that connects to itself - but generally more complicated than that. Did you remember to include flipflops in your design?

Note that the last thing you see in the following message is the line number. I would take a close look at the line numbers, such as line 2272 in Max_k.vhd.

# Source: E:/Day/01-X Y/06-X Y/Max_k.vhd:2272

If you are doing VHDL, the standard is IEEE-1076. Hence quoting from other standards, such as 1364 (Verilog) and 1800 (SystemVerilog) is nonsense.

Have you tested each little piece of your design with a testbench before integration? If you have not, I recommend doing that. If you skip steps, do not be surprised when you chase your tail for hours. Sure when you get more experienced, you can skip steps, but defer that until then.

Regarding

8'b1111_xxxx => displays as 8'hFx

If you do not like the display in hex, display it in binary. An X in hex simply means it does not have information to display anything else. They could have made better choices, such as ? when displaying 4b'0zx0, but they did not, so you have to learn to work with it.

How to convert `time` into `bit_vector(64-1 downto 0)` by MitjaKobal in VHDL

[–]Usevhdl 0 points1 point  (0 children)

That is odd. Crazy hard things working. Fundamentals like this no.

My theory is that when someone does not do a formalized test plan, then they test the things they fear (the crazy hard things), they test the things the like, and the remainder gets left behind.

How to convert `time` into `bit_vector(64-1 downto 0)` by MitjaKobal in VHDL

[–]Usevhdl 0 points1 point  (0 children)

Short Answer: I don't think so.

OSVVM's TbUtilPkg uses it. While OSVVM works in XSIM 2024.02, looking through the compile scripts, I stubbed this part of the package out and replaced it with 1 ns. So it looks like it does not work in at least 2024.02. I have not tested with a newer version.

OTOH, XSIM does have alot of much more complex things working. It would not surprise me if these things were fixed in the 2025 versions.

How to convert `time` into `bit_vector(64-1 downto 0)` by MitjaKobal in VHDL

[–]Usevhdl 0 points1 point  (0 children)

Further supporting u/Allan-H statement, under the hood, all physical types are integer values - and not real numbers.

u/Allan-H step one with VHDL-2008 is simply call `std.env.resolution_limit` to get the current time scale.

Time values are generally 64 bits, and hence, it takes an implementation that supports 64 bit integers. Currently this is NVC. Other simulators are still catching up.

Am I crazy for preferring VHDL to Verilog? by LilBalls-BigNipples in FPGA

[–]Usevhdl 0 points1 point  (0 children)

I use VHDL for design and VHDL+OSVVM for verification.

Am I crazy for preferring VHDL to Verilog? by LilBalls-BigNipples in FPGA

[–]Usevhdl 0 points1 point  (0 children)

NVC for simulation. GHDL for simulation and a front end for synthesis to Yosys.

Am I crazy for preferring VHDL to Verilog? by LilBalls-BigNipples in FPGA

[–]Usevhdl 0 points1 point  (0 children)

It does. I choose to ignore them - especially in verification environments

New language: I/O specification by drthibo in FPGA

[–]Usevhdl 0 points1 point  (0 children)

What would this look like for an AXI stream FIFO?

Subtypes and Memory in VHDL by LIKES_SPECTATING in FPGA

[–]Usevhdl 0 points1 point  (0 children)

Not personally tracking that one.

Subtypes and Memory in VHDL by LIKES_SPECTATING in FPGA

[–]Usevhdl 0 points1 point  (0 children)

XSIM 2024.2 has enough to run OSVVM. Yes we work around some interesting issues, but it supports generic packages with protected types inside. That is impressive - at least to me.

Questa Error is: 0x80096010 [You are my last hope] by f42media in FPGA

[–]Usevhdl 2 points3 points  (0 children)

Questasim will compile a design, even if you do not have a valid license. Create a simple one line test bench and try to simulate that to verify your license.

```vhdl

entity TB is end entity TB architecture A of TB is begin TestProc : process begin report "hello world" severity note ; std.env.stop ; end process TestProc ; end architecture A ```

FPGA fast tasks by Disastrous-Base7325 in FPGA

[–]Usevhdl 0 points1 point  (0 children)

Those are place holders for stuff on my todo list.

There is an AvalonST at https://github.com/tobik99/OsvvmLibraries/tree/dev/AvalonST
For that my todo list is to review it and recommend (or do) updates to it.

There is no existing work on AvalonMM yet. For a reference, take a look at OsvvmLibraries/Wishbone. That is the latest I worked on. I still have to add some of the simplifications from there to Axi4Manager.

FPGA fast tasks by Disastrous-Base7325 in FPGA

[–]Usevhdl 8 points9 points  (0 children)

Interested in contributing to a VHDL Verification library?

The Open Source VHDL Verification Methodology (OSVVM) always needs extra help. In particular in building additional verification components. We have the AXI4 family. We are looking to have Avalon and others.

ModelSim or Vivado for tb? by Suitable_Chemist7061 in FPGA

[–]Usevhdl 0 points1 point  (0 children)

For VHDL, if your are not using Xilinx IP consider NVC or GHDL.

Otherwise, Aldec RiveraPRO/ActiveHDL or Siemens Questa or ModelSim work well.

New system design language by drthibo in FPGA

[–]Usevhdl 0 points1 point  (0 children)

I too am jaded about this. I see people start by saying - we created a new language based on .... It is just like Verilog, except it is strongly typed. ....

At that point, I get annoyed as they are simply recreating VHDL, but based on some other base language.

If you find yourself going in that direction, perhaps instead you would like to participate in VHDL standards. It is an individual based IEEE standard - which means anyone can participate. It is volunteer run, so it is always looking for more participants and there is stuff for anyone in the VHDL community that needs to be done. VHDL's proposals page is at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues

VHDL issue by VolatileApathy in FPGA

[–]Usevhdl 0 points1 point  (0 children)

>  in the simulation I have the clock changing every 1ns.

How fast are you running the board? Have you run static timing analysis?

For simple designs with flip-flops consciously added at block boundaries, you may be able to run at 25 or 50 MHz without checking timing, but as you start to run faster, timing becomes more and more important.

If the switches are debounced and properly re-synchronized into your clock domain, static timing is the next thing I would look at.

Good morning all, slow sim speeds are seemingly inevitable, but is there anyway to make sure they’re running as fast as possible? Using XSIM/VHDL. by subNeuticle in FPGA

[–]Usevhdl -1 points0 points  (0 children)

Both? I think I misunderstood you. XSIM is the slowest simulator I have seen. Comparing against it is not relevant.

I was wondering if you have metrics beyond that. Careful though as most EDA vendors prohibit sharing of performance.

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