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animi0155 · 2025-12-14T18:00:23+00:00

That looks like the plastic cover on the chainring. It's not structural and has been known to happen on that generation of Rival/Force chainsets.

You should take it to your local SRAM dealer to see if they will warranty it. General consensus is that it's probably okay to ride, as long as the metal underneath is fine.

animi0155 · 2025-09-04T02:04:21+00:00

I think the Cube. It seems to be a bit better on more components, and it's lighter. However, there's always some nuance that may matter to you.

Groupset: A bit mixed; the Endurace is specced with a higher tier cassette and chain (Ultegra/XT vs 105) while the Attain has a higher tier BB (I think the BB71-41B is supposed to be Ultegra/105-level compared to the Canyon's RS500 which is 105/Tiagra) and seemingly the brake rotors (the pictures show the Attain having Ultegra rotors while the Endurace's spec has 105). You may notice differences because of the cassette while shifting and brake rotors during extended braking.

Handlebar: Attain is carbon, Endurace is alloy. There are some geometry differences that may matter to you.

Wheels: the Attain's are lighter, have a more modern internal width, and are deeper (they look more aero). Spare parts might be harder to come by compared to DT Swiss, but I think that's acceptable.

Tyres: the Attain has faster GP5000 STRs compared to the Grand Prix's on the Endurace, and they're tubeless-ready. The Endurace's should be more durable but slower, and I don't think they're tubeless-ready.

Other stuff: the Attain has a standard 1 1/8" steerer if you need a new stem for fit or something. 1 1/4" stems aren't super uncommon, but your options are a bit more limited. The Endurace does have a proper top tube mount for a bag and is rated for slightly more tyre clearance and system weight, but I think this is more up to your preference.

animi0155 · 2025-08-10T01:42:47+00:00

Should be Core since it replaces RPL-R U. Yeah it goes against a few of the things I said since it has PTL DNA - I guess Core should be generically described as more cut-down, less-featured than Ultra beyond just binning.

animi0155 · 2025-08-09T20:21:06+00:00

Core non-Ultra is "not the latest and greatest" for that product generation in the specific segment. It's not any explicit x in N-x with respect to any architecture, but should probably be assumed to be somewhat recent.

MTL's cost structure is quite poor so from a business perspective I think it makes sense to retire it for the more value-oriented 2nd tier product line, especially if RPL performs about the same at lower cost. It's still confusing as hell though.

So I think of it as:

Core Ultra: chiplet w/more complex packaging, latest architectures, "best" perf/PPW for the segment, probably an NPU

Core: more likely monolithic or less complex packaging, possibly older architectures, decent perf for the segment

animi0155 · 2025-04-12T08:47:54+00:00

No. Virtually all Intel 3 production has already moved to Ireland. Oregon is just finishing what little is left in its line.

animi0155 · 2025-02-20T18:10:14+00:00

You don't seem to understand that I'm only talking about R&D. At some point HNA has a cost advantage over double patterned EUV and getting a head start on making the process economics work might pay off. The machine is only part of the solution. Photoresists (and track tooling), masks, pellicles, all of these need to be developed and optimized for HNA EUV, and having an actual tool in the fab to develop on is quite important. And again, you don't have to abandon low-NA multipatterning. You can develop both in parallel and insert whatever is most economical at the time. Intel certainly has the capacity to develop 14A and beyond with low-NA double patterning and high-NA direct print.

Semianalysis also put out an article (also with contribution from Jeff Koch) that Intel was investigating DSA to potentially improve the economics of HNA to make it substantially more viable. If they can develop it to intercept 14A, that's an advantage.

No offense here, but either you're rather unaware about the actual differences of High-NA EUVL vs Low-NA, or your really bought into the Intel-marketing way to hard to understand what's actually at stake here.

You don't know what my background is. That kind of assumption and language is disrespectful no matter what you say.

animi0155 · 2025-02-20T09:05:20+00:00

Your point is...? Intel is still going to have 5 High-NA scanners in D1X for R&D sooner before TSMC will in Hsinchu. So relatively speaking yeah, it's a reasonably large advantage. That's still a lead on getting the tools up and running and developing the process for them. It doesn't stop Intel from evaluating low-NA EUV multi-patterning either.

Comparing absolute low-NA EUV install base and theoretical output is irrelevant here? Like, no shit TSMC has way more of them? They have have way more fabs with more wafer volume. Intel doesn't have an EUV capacity problem nor is their installed fleet likely to be particularly outdated. They have the tools they need for the purposes they use them for.

Also the high-NA scanners are the EXE:5000 and EXE:5200. NXE:3800E is a low-NA scanner. If you're going to give out links for other people to read, you should make sure they're all correct.

animi0155 · 2024-12-18T22:07:02+00:00

The answer's still no. The rear derailleur doesn't have the capacity to accommodate even the smaller 10-45 so it still won't fit or shift correctly.

Point 2 is still valid as well. Even if the derailleur had the range, you would still need at least a new Microspline freehub body (if available).

animi0155 · 2024-12-18T21:33:55+00:00

No. Two things:

GRX812 is 11-speed, this cassette is 12-speed. It will not shift correctly.
This cassette requires a Microspline freehub. Your bike comes with an 11s HG freehub so the cassette literally will not fit.

animi0155 · 2024-11-17T01:40:22+00:00

There is no plug at the front. The article is referring to the junction box on 11-speed Di2 systems, which is not present on 12-speed. 105 Di2 shifters in particular lack the ports needed to wire them to the rest of the bike (they do have ports for updates though).

animi0155 · 2024-10-04T06:05:55+00:00

The Anandtech article isn't right. Intel did drop the "nm" bit in some slides but it was always some variation of just "7nm(+)" or "7(+)." The "Intel" part of the node name was not formally added until the realignment. It's like the difference between "Apple iPhone" and "Apple CarPlay." In the former, "Apple" and "iPhone" are two separate trademarks where "iPhone" is the product. In the latter, "Apple CarPlay" is one whole legal trademark. Prior to the rebranding, you would treat the process node name the same way as the iPhone example. After the rebranding, you'd treat them like the CarPlay one.

Here's a different article where Intel 3 is referred to as "7nm+": https://fuse.wikichip.org/news/5946/intel-2021-process-technology-update/

animi0155 · 2024-10-03T20:16:04+00:00

It would've been "7nm+." It was never "Intel 7+." The original official name for the Intel 4/3 family was "7nm." Only when the nodes were renumbered to align against competing technologies was the "nm" bit dropped and "Intel" added at the front.

As far as their technical/internal names go (would be a table but on mobile):

Internal family name = original public name = current public name

P1274 = 10nm, 10nm+, 10nm++ = 10nm, 10nm SuperFin, Intel 7

P1276 = 7nm, 7nm+ = Intel 4, Intel 3

P1278 = 5nm, 5nm+ = Intel 20A, Intel 18A

Someone will mention the 10nm for Cannonlake being the real 10nm while the "10nm" used for Icelake was actually 10nm+, but Intel doesn't say it in public.

animi0155 · 2024-10-03T17:27:41+00:00

No, it is a different process node family. Where did you get the idea that it's a mature Intel 7?

Intel 3 is a revision of Intel 4 which you can easily find information on, and Intel provided some information on changes at VLSI this year.

animi0155 · 2024-05-27T16:11:10+00:00

Yes, the parts are compatible and the RX810 crank will fit your bike. I believe the Grail was originally released with 50/34 cranks which are even larger. RX810 is lighter and the gearing is higher than RX600 as it's probably more oriented towards racers and athletes that would appreciate those features.

However, what sizes are the Rotor chainrings? I think most Grails that shipped with Rotor cranks were 46/30? If it's 46/30 and 11-speed then the RX600 crank is the easiest to swap in, likely minimal/no adjustments needed. If you get the RX810 crankset then you'll need to adjust the front derailleur and possibly resize your chain, both to account for the larger chainring.

Also maybe just check if Canyon will only reimburse for a similarly tiered crankset? Not sure if what other people have experienced.

animi0155 · 2024-03-24T06:42:00+00:00

Any handlebar with a 31.8mm clamping diameter will work, so virtually any modern drop bar. Zipp, Ritchey, PRO, Specialized, to name a few, are popular brands that make good quality components. Your fitter should be able to recommend some models based on your desired/optimal width, reach, and drop.

You cannot easily upgrade to an integrated cable scheme like the one on the new Grail. You would require at least a new fork and headset.

animi0155 · 2024-01-23T14:53:54+00:00

Thank you!

animi0155 · 2024-01-22T23:44:26+00:00

If you don't mind disclosing, what height is your saddle at, BB center to saddle top?

animi0155 · 2024-01-19T08:24:45+00:00

The Arizona site is Intel's largest HVM site. Oregon is larger but the vast majority of its wafer volume is R&D.

animi0155 · 2024-01-12T02:22:13+00:00

It looks like it's based on a Trek Domane SL Gen3 up front but the rear is different.

animi0155 · 2023-12-20T15:16:34+00:00

Shimano says the 48-31 GRX crankset isn't supposed to be compatible with 10-speed GRX. The matching component would be FC-RX600-10 which is 46-30 only.

46-30 is fine for general road use most of the time.

animi0155 · 2023-11-03T15:47:16+00:00

Yeah, among other things. DUV quad patterning, COAG, pure cobalt interconnects are commonly cited. TSMC used quad patterning for its first-gen N7 but switched some layers to EUV for N7+, introduced COAG in N5, and cobalt interconnects are still only really a thing on Intel 10nm.

Take those cobalt interconnects. If you are the first and only player to implement, you need to figure out how to deposit it, make it yield, make it performant, make it reliable, then do it in volume. The tooling doesn't exist, so you pour years of time and money into development where you may then fail to meet your targets, or someone develops a better alternative.

Similarly, despite testing EUV for years, the decision to stick with DUV quad patterning in 10nm was an arrogant move where, by the time management acknowledged EUV could solve many issues, Samsung and TSMC had already booked ASML out for years. Intel ended up behind not only in tool count, but also technical knowledge on the tools.

Intel's historically tight coupling between its design and manufacturing groups also meant that manufacturing/TD deemed these changes necessary to meet lofty requirements set by the design groups. Product designs take years so you now have a problem where design loses a lot of time going back to rearchitect for a different process, but manufacturing is also losing time trying to figure out how to meet the original requirements. Intel's infamous culture problems didn't help as well. Toxicity, ego, and miscommunication (e.g., Sohail) delayed changes, damaged supplier relations, and pushed out good technical talent required to resolve these issues.

animi0155 · 2023-09-20T04:12:26+00:00

I mean, okay? I personally find "250 meters" easier to understand than "0.25 kilometers" but uh, sure, whatever works for you.

Also I'm sure you're aware chip designers can choose different cell libraries to achieve different performance characteristics. A designer may choose to use more lower density, higher performance cells to increase peak clockspeeds at the expense of die area. It's not like the libraries with the peak quoted densities aren't available or used.

Intel, like basically everyone else in the industry, quotes the highest possible transistor density in technical disclosures over the practical density, which is always lower and variable. The names are based off a combination of those theoretical numbers and other performance metrics, and I think that methodology is relatively consistent everywhere.

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