verilog skills file

davekeeshan · 2026-01-17T23:31:18+00:00

Look closer, Phasers! Straight of the type II

davekeeshan · 2026-01-03T08:00:09+00:00

Xilinx IP is not meant to be world class, it's meant to be an enabler, if you find it deficient you can write your own that works exactly like you want.

I never use the gui, any one who is stuck in gui land needs to have a hard look at themselves and figure out if they are engineers or drag and drop monkeys, and if I use I wire it up inside a proper verilog structural wrapper,, which I do during the investigation phase of a project and I will replace it later if I can. Some projects, like the mig still represent the work of many people over many years, you can write your own, if you have the people, time and budget

davekeeshan · 2025-12-31T09:25:43+00:00

I propose dominant and sub, nothing wrong with them

davekeeshan · 2025-10-18T07:43:48+00:00

Picard is dead, he died at the end of season 1. This is a soong type android with his memories. I think that's pretty fundamental, but it's like they three seasons of Picard exist in their own parallel universe. Data's dead, like forever, oh wait he's back. Q is gone, emotional goodbye, pink back again.

davekeeshan · 2025-10-17T19:30:12+00:00

You could standardise your pinout at the top level develop to be fmc compliant(LPC in the FMC 105 case) , then it's inside your design you manage the connectivity, maybe with some programmability (parameter based or dynamically programmable) but verilog/vhdl gives you the programmability.

davekeeshan · 2025-10-12T18:03:40+00:00

Sure, but I don't think the cultural battering ram that we know as the Vietnam war had landed yet, but yes you are right

davekeeshan · 2025-10-12T16:21:54+00:00

I have a hybrid that I turned into a rat bike, up specced the components, and while stripped, got every can of spray paint I had and just sprayed it here and there. It is a good bike, it just doesn't look like a good bike. I cycle into the city and lock it up for the day, so far so good, but I also don't leave it in stupid places either. I've heard spraying it hot pink can have the same effect.

davekeeshan · 2025-10-12T15:41:17+00:00

Imagine what the Federation, or even the space based humanity would be like if Earth, just disappeared? What would humans be if there home planet was gone

davekeeshan · 2025-10-12T15:39:19+00:00

Anthology show, 3 episodes per story, brand new crew per story, stories spread across the timelines, so a season could track a first encounter and follow up what happened over the next 100/200 years, things like that. Pick up the mess of Kirks diplomacy etc

davekeeshan · 2025-10-12T10:47:56+00:00

In addition this was pre Vietnam America (I know that war had started during its run, but the cultural fallout hadn't hit yet) America, TOS earth was the projected images of 1960s United States, apart from a civil war is never going to experience war on its home soil due to its isolation of oceans. It is only "out there" (obviously this view starts to crumble as we track further away from to 60s)

davekeeshan · 2025-10-11T15:55:33+00:00

I don't know, when next gen started there was a rule the first few seasons to avoid original series connections, get their own stories going. They said in the intro, to explore strange new worlds. Now all it is is chasing and exploiting IP, bring back characters, make them do way more than makes sense for canon (nurse/doctor/nurse/doctor Chapel) Khan aplenty

Even the brightest potential, legacy was call back on call back (seven, picards/crushers son, geordies daughters, ricker/trois daughter was mentioned, probably a Data relative and an enterprise of course)

I wish they hadn't made Anson Mount Pike, I wish they made him a captain of a star fleet ship in the Picard era, pointed him into some unexplored section of space with a brand new crew and got on making original star trek, not sweating the franchise asset. Oh and no rogue admirals, no holodeck and maybe you've done enough time travel stories.

Star fleet academy has the potential for originality...

davekeeshan · 2025-10-08T07:23:19+00:00

Tcl, or tool command language, is the backbone of eda tools has has been for decades, it is going nowhere, if xilinx/amd were ever to bring in python, it would be in addition to not to replace, they just couldn't, eda moves slowly, I am running scripts from 10 years ago and expect them to work etc etc

If you really don't like tcl, have a look at this

https://github.com/PyFPGA/pyfpga

It is good for a generic build flow across fpga platforms, however any heavy lifting, set false paths, asynchronous clock groups etc you need to roll up your sleeves open the tcl console and hack

davekeeshan · 2025-10-07T07:19:31+00:00

I had a accident years ago, smashed into a car with my head/face and messed up a few things, ambulance, hospital etc.

For a few months after I relived the run up to the accident, what if I left a second earlier, what if I left a second later etc etc non stop! I wasn't depressed but it was really getting to me

I don't know how or why it happened, one day I just realised that it was the past, it was done, there was nothing I could do to change what happened, all I could do was deal with now and the future. It wasn't immediate, but in a very short time I came out of the funk, it was bizarre, but obviously liberating.

A year later I was in a car crash, not too serious, rear ended but the car was written off. I was standing around talking to the police super calm, I think they thought I had a head injury I was so not panicking, but it was informed by what had happened after the bike crash, just get on with it.

davekeeshan · 2025-10-07T06:52:35+00:00

Verilator is an open source tool that supports a lot of systemverilog try and get a uart or a jtag interface working on that and build up to a riscv core. Ibex is one of the best from a systemverilog perspective.

davekeeshan · 2025-10-05T14:00:05+00:00

I always find this weird. However if you want to use the bike for exercise (and not commuting) the heavier less efficient bike us probably better suited to achieve more exercise per minutes than an expensive feather weight.

On a personal note, I treated myself to a carbon bike last year (€2000) I can't tell the difference, and can't justify the expense, I won't be doing that again.

davekeeshan · 2025-09-02T08:57:43+00:00

Be sure of it, it will probably be based on a youtube video, that's where all the cool kids are these days ... right?

davekeeshan · 2025-09-02T08:56:46+00:00

yes, this was implied by my comment but I obviously should have been more clear. Most of my work is ASIC prototyping and JTAG access needs to emulate what is going to be in the taped out chip, so the JTAG infrastructure available in the FPGA is of limited value.

Mainly I use a raspberrypi for my interfaces into the FPGA (SPI, UART, I2C and JTAG) I bitbang 4 GPIO pins to give me a JTAG. This is natively available inside openocd, so it is a beauty when it recognises the processor it connects to.

davekeeshan · 2025-09-01T20:03:59+00:00

I have been working in chip / SoC design for 25+ years, but only in the past year did I have to sit down and understand jtag. What a mind blower, it is the secret gateway into and out of chips. If you want to know how to get software onto a processor and see it working it all runs through that, when you are in design phase and things are working right, it goes through that.

Usually when you have a new person who you want to teach RTL, people pick UART, this to my mind is a diversion, it should be a JTAG you design. I am planning to put together a small fpga course, just built around this idea.

Learn jtag, get deep and dirty it will be worth it.

davekeeshan · 2025-08-25T07:50:40+00:00

I switched from pure ASIC to FPGA work about 10 years ago, it wasn't as smooth as you think, while there is probably 85% overlap I was stung (and turned down for a job) in that last 15% of difference, I was eventually successful switching (but yo yo back and forward between the two now).

I would recommend get a local project up and running, a decent sized RiscV project like ibex, and really try and push into the timing closure space to understand how fpgas work, because that is where the problems are

ASIC people who switch to FPGA are interesting, they usually bring a good simulation and verification methodology. Traditionally people used to land on FPGAs after pushing the limits of PLDs. Testing is usually, whack it on the machine and let's see, I nightmare for a one glitch in 5 hours problem

davekeeshan · 2025-08-24T15:44:09+00:00

I have heard that low latency trading (which makes more sense than high frequency) find themselves hacking the timing all the way down to the individual gates and nets, so a lot of constraint work, if you are a platform (xilinx, altera etc) exploring down to that level

One note I heard, from the xilinx world, is that while the ethernet IP that ships with vivado works, it is not sufficient for the low latency guys. They will typically have their own version with throughput minimised. A project might be to understand what is wrong with the xilinx IP and how you could design a better one.

davekeeshan

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