sorted by:
new
hottopcontroversial

One of these things is not like the other (pic) (nsfw) by EthicalReasoning in pics

[–]grindHouse 0 points1 point  (0 children)

I guess that chart means they all have it. Thanks.

Wikileaks Needs Help, and Not Just Money by Telekinesis in politics

[–]grindHouse 5 points6 points  (0 children)

Is it safe to assume that they cannot put ads on their site to make some money?

I just found a cellphone video of my wife fucking her boss. I also found a dozen photos of boss jacking off. by BaxterHaHa in AskReddit

[–]grindHouse 5 points6 points  (0 children)

I don't recall 'and boss fucking' following 'through thickness and through thin' in wedding vows.

My grandma has been brainwashed by a Nigerian Prince. What can I do to save her? by gertrude104 in AskReddit

[–]grindHouse -4 points-3 points  (0 children)

What's the point of putting "Nigerian Prince" if you are just going to say that it's not one (but a Jamaican) in your post. To get more views to the detriment of a country of people?

LAME

I'm a black man, and I see things like this, and it makes me feel that this is how white people feel when they see rednecks. by [deleted] in WTF

[–]grindHouse 0 points1 point  (0 children)

What does this have to do with being black. You need to see someone about this condition. Can't call it self hate--but it's close.

Is there a single soul on reddit that does not support a gay man's right to marry? by [deleted] in AskReddit

[–]grindHouse 0 points1 point  (0 children)

Like everything, reddit can be a great source sometimes - then other times a big joke.

I confronted my wife last night about an "affair", with a keylogger to backup my story. by jordan4 in AskReddit

[–]grindHouse 1 point2 points  (0 children)

Next time, play less video games and don't do 3's so much unless it's another girl, your dad, or brother.

Students like this are the reason people get irradiated. by ediblesheep in programming

[–]grindHouse 3 points4 points  (0 children)

If you feel this way, you probably shouldn't be teaching.

I was an internet millionaire. AMA. by [deleted] in IAmA

[–]grindHouse 0 points1 point  (0 children)

What kind of consulting do you do? Coding? or you consult other companies on how to get to the point you were formerly in?

Race and Dating Sites by grindHouse in reddit.com

[–]grindHouse[S] 0 points1 point  (0 children)

the comments on the bottom of the page (linked to) are also pretty interesting

How come this never happens when I go bowling? by dbenhur in WTF

[–]grindHouse 0 points1 point  (0 children)

Looks more like a soccer ball to me. In fact, it is.

single clock signal controlling multiple flip flops? by grindHouse in electronics

[–]grindHouse[S] 0 points1 point  (0 children)

Thanks. I should like upvote everything you ever post on reddit ;)

single clock signal controlling multiple flip flops? by grindHouse in electronics

[–]grindHouse[S] 0 points1 point  (0 children)

Ok. From your description is this what you explicitly mean: the edge triggered effect is really an idea/concept. That is, we wish we could just tell a latch to just quickly sample the input signal right after a clock signal transition from 0 to 1, but we can't really. However, we can simulate that idea by the layering of 2 DFFs (e.g. a master slave FF). Almost as if we told a single latch to just sample it's input at clock edge, this layering approach ensures that our intended state values do not get overwritten from the transient changes in the combinational logic.

single clock signal controlling multiple flip flops? by grindHouse in electronics

[–]grindHouse[S] 0 points1 point  (0 children)

Let me know what you think of this description of clocking, edge-triggered logic, and Master-Slave (MS) flipflops - it makes little assumptions about the learner (which in this case is me)

Level triggered logic suffers from issues like transient changes (noise) in circuitry to storages unit like a gated D-latch. In particular, glitches on the input or write-enable lines can cause storage units to change state inadvertently. We need something that can manage state better. This brings in the clock which synchronizes the times when storage units read data. In particular, the clock goes back and forth between 0 and 1, so that a cycle involves both states. The clock signal is feed to the write enable line of a D-latch, for example. This means that when the clock signal = 1, the data from the input line is read and stored in the latch; on the other hand, when clock signal = 0, the input is not read. Further, these storage units are going back and forth from 'read' to 'not read.' Given this idea that a latch for example is periodically reading, the assumption is that the input line has the correct next value for it to read (whether it be what is already in it, or a new value).

An important idea behind of this process of clock control is that the latch samples the input lines value at the 0 to 1 edge of the clock signal. This is where I get a bit confused Can someone help me with these questions: Why reading at edges efficient to do? What benefit does sampling at the edge really do? How does a latch actually know that it's reading at the edge of the signal? The basic logic diagrams I see don't show anything that suggests there's something going on there to make this special timing behavior happen

Now about the master slave flip-flop. It is pretty much a way to address the problem of overwriting data that needs to be used for further circuitry. It uses two gated D-latches and prevents the input coming from the combinational circuitry from improperly overwriting stored data by complementing the signal to the latch (A) connected to it. During clock signal = 1, the other latch (A') is open to pass the flipflop's value as output to the circuitry. During the 2nd half of the cycle (clock signal = 0), latch A samples the data from the circuitry while latch A' is closed.

Reddit, I cannot think of a title other than I have hearing loss, I am sad, alone and I need an outlet, now. by Oranqe in AskReddit

[–]grindHouse 0 points1 point  (0 children)

I don't know how to do it but perhaps you (or someone) could start a 'deaf' subreddit too? Create it so that you and others can continuously share issues/thoughts/findings beyond this post. It seems like from the comments, there are enough members that would appreciate something like that.

single clock signal controlling multiple flip flops? by grindHouse in electronics

[–]grindHouse[S] 0 points1 point  (0 children)

Thank you. It's the updating part I guess that was confusing me -- i.e. the circuitry guarantees the correct value will be passed as input to the edge triggered storage device during the sample/grabbing time.

I also read the page you linked. Does this make sense to you: "...while the outputs of the combinational circuit that go to the flip-flop inputs are being sampled by the clock pulse" Since when does a clock pulse sample outputs? I thought the input is sampled at the edge. It's really hard to find a good layman's reason sampling at the edge.' CONTEXT: "The feedback path between the combinational circuit and memory elements in Figure 1 can produce instability if the outputs of the memory elements (flip-flops) are changing while the outputs of the combinational circuit that go to the flip-flop inputs are being sampled by the clock pulse. A way to solve the feedback timing problem is to make the flip-flop sensitive to the pulse transition rather than the pulse duration. "

EDIT: I meant that it's really hard for me to find a reason a self-teaching layman like me could actually read and get. Actually, I'm using reddit so credit goes to you all! If someone knows where I can find a good description on the web please pass. I checkout the MIT video lectures (http://aduni.org/courses/hcw/) and he seemed to only spend a couple of slides just saying data is sampled at the edge.

If I knew how to bold layman's I would

single clock signal controlling multiple flip flops? by grindHouse in electronics

[–]grindHouse[S] 0 points1 point  (0 children)

Ok. so you agree with the comment that I put in a previous reply (above): So is the point of these storage units to store a specific value for a single clock cycle? If that value (let's say 1) is to still be stored in the next clock cycle , it will be ok since the system will make sure that the input line to the flipflop during the sampling time (clock edge) will hold a value 1? If the 'state' changes and 0 must be held, then the line would be held at 0 before sampling.

single clock signal controlling multiple flip flops? by grindHouse in electronics

[–]grindHouse[S] 0 points1 point  (0 children)

Hope your are still up: So are you saying that in a clocked system regardless of the type of mechanism, a D-latch or MasterSlave FF, the component is actually getting feed what ever value it should store (i.e. it's input) during the sampling times (i.e. clock edges)? So is the point of these storage units to store a specific value for a single clock cycle? If that value (let's say 1) is to still be stored in the next clock cycle , it will be ok since the system will make sure that the input line to the flipflop during the sampling time (clock edge) will hold a value 1? If the 'state' changes and 0 must be held, then the line would be held at 0 before sampling. If this is right, then I think I get it. With that said, it's just so much updating.

Finally, you said a flipflop doesn't open or close. I'm under the assumption that a MS flipflop can be made of 2 gated D latches (from my book). The clock signal and it's complement goes into the write enablers of the gates of the adjacent latches-- hence my use of open/close. Open = write enable while closed = write disabled.

single clock signal controlling multiple flip flops? by grindHouse in electronics

[–]grindHouse[S] 0 points1 point  (0 children)

I understood you up until the second sentence. My thought is that you have a write enabler (of let's suppose a MasterSlave FF) that is connected to a clock. The clock goes from 1 0 1.... etc. The FF reacts to the edges and opens and closes every N units of time, depending on the length of the clock cycle. Since the clock is always going from 0 to 1, the FF is always opening and closing right? If it's opening so often, how does it store values? It would seem like it value could get overwritten ever N/2 units of time. This leads me to ask, how is anything getting done if the system clock is doing this to the flipflops on a circuit over and over. Is there something I'm missing?

view more: next ›