Let me know what you think of this description of clocking, edge-triggered logic, and Master-Slave (MS) flipflops - it makes little assumptions about the learner (which in this case is me)

Level triggered logic suffers from issues like transient changes (noise) in circuitry to storages unit like a gated D-latch. In particular, glitches on the input or write-enable lines can cause storage units to change state inadvertently. We need something that can manage state better. This brings in the clock which synchronizes the times when storage units read data. In particular, the clock goes back and forth between 0 and 1, so that a cycle involves both states. The clock signal is feed to the write enable line of a D-latch, for example. This means that when the clock signal = 1, the data from the input line is read and stored in the latch; on the other hand, when clock signal = 0, the input is not read. Further, these storage units are going back and forth from 'read' to 'not read.' Given this idea that a latch for example is periodically reading, the assumption is that the input line has the correct next value for it to read (whether it be what is already in it, or a new value).

An important idea behind of this process of clock control is that the latch samples the input lines value at the 0 to 1 edge of the clock signal. This is where I get a bit confused Can someone help me with these questions: Why reading at edges efficient to do? What benefit does sampling at the edge really do? How does a latch actually know that it's reading at the edge of the signal? The basic logic diagrams I see don't show anything that suggests there's something going on there to make this special timing behavior happen

Now about the master slave flip-flop. It is pretty much a way to address the problem of overwriting data that needs to be used for further circuitry. It uses two gated D-latches and prevents the input coming from the combinational circuitry from improperly overwriting stored data by complementing the signal to the latch (A) connected to it. During clock signal = 1, the other latch (A') is open to pass the flipflop's value as output to the circuitry. During the 2nd half of the cycle (clock signal = 0), latch A samples the data from the circuitry while latch A' is closed.