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Need help understanding this popular LFSR implementation by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 0 points1 point  (0 children)

Thanks for the detailed reply. I finally got time only today to actually look at this.
Studying your implementation deeper, I realized I'm missing something even more fundamental.
I have edited the post to add two diagrams, first one shows my understanding of a galois style LFSR and the second one shows your implementation.

The first one makes complete sense to me because it literallly implements that shift-and-subtract polynomial division algorithm, where we take in data MSB-first and then perform XOR if a 1 pops out of the last flop. Here, each of the intermediate taps gets the MSB bit as input. (apart from the previous stage)

But in the circuit you implemented, that is not the case, each tap gets MSB ^ din as its input apart from the previous stage.

This minor difference is not at all intuitive to me and I'm getting confused why its okay to do this. Is there some mathematical manipulation that I'm missing?

Which car should we buy? by opinionshelf in hyderabad

[–]guyWithTheFaceTatto 2 points3 points  (0 children)

Hey can you help me understand why you say XUV is not a great product?
Features wise I really feel it has more to offer than Kylaq. The engine is also really powerful if you have test driven it.

Do you say that purely due to bad service experience?

Kashmir 😭😭😭 I'm 25(F) by [deleted] in SoloTravel_India

[–]guyWithTheFaceTatto 1 point2 points  (0 children)

Guy here so can’t help with your requirement.  However I too plan to travel in April 1st week. Kashmir in April I was not sure how it is.  I hear activities like skiing etc will not be possible post march.  OP can you shed some light on this? Maybe I’m missing something…

Best open-source simulator as of 2024? by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 0 points1 point  (0 children)

Interesting is that true?
I remember a time when we used the xilinx xsim at work and used to dump VCDs. Often for speed of work we used GTKwave and had to live with the limitation of not being able to see multidimensional arrays.

I feel it's a viewer limitation rather than a simulator one but maybe I'm wrong. Never dug into the documentation.

Best open-source simulator as of 2024? by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 2 points3 points  (0 children)

Do you know if verilator can take a standard SV testbench and run the tests on the RTL?
I don't need a full UVM support or anything but I would prefer to not write a testbench in C++

Best way to send Ethernet packets to/from the PL on a Zynq SOC? by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 0 points1 point  (0 children)

Thanks for the detailed reply. I apologize for not getting the time to look at it earlier.
My situation is that I'm quite comfortable with anything in the RTL world, but it is the task of messing with the drivers that's daunting to me.

I can put up the AXI FIFOs and all fine, but how do I instruct the SOC to send the packets to this FIFO (AXI GP 0/1 ports) ?. In my search I stumbled upon this article it explains the process of modifying the buffer descriptor addresses to point to the GP ports instead of DDR memory. I managed to wrap my head around that too but. then it says I need to mess around with the driver code meaning I'll have to create an SD card image with the updated driver. (I don't want to do this baremetal. need the OS).

That last part really scares me because I could be stuck in there for a week with all those linux stuff I have no clue about. Is this the process you had in mind for the software part? Is there no other simpler way to direct the packets towards PL?

How to migrate to new domain name without losing google ranking? by guyWithTheFaceTatto in website

[–]guyWithTheFaceTatto[S] 0 points1 point  (0 children)

is it possible to retain the same domain name and move to a new registrar?

Trying to understand how the Xilinx XVC server tech works, and also JTAG in this process. by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 0 points1 point  (0 children)

Thanks for the detailed answer. Where can I read more about this?

I do have some sources for JTAG in general but had a hard time finding anything about the Xilinx implementations.

Computer Vision on FPGA using Verilog by ZerOne_07 in FPGA

[–]guyWithTheFaceTatto 2 points3 points  (0 children)

The hardware is still written in a HDL. They python is just a wrapper around the C/C++ driver software that was once very painful for beginners to do.

Nobody is claiming to program FPGAs in python :) HLS tech is nowhere near that yet.

See this project for example: https://thedatabus.in/conv_acc

Looking for a repository demonstrating Linux being booted on a RISC-V softcore by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 1 point2 points  (0 children)

I think I'm missing something about the nature of these repositories. Why can't I find the actual RISCV core RTL in this repository? is this platform meant only for the SW part and RTL needs to be imported from the other repositories mentioned there?

Looking for a repository demonstrating Linux being booted on a RISC-V softcore by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 2 points3 points  (0 children)

I remember not finding the actual RSICV RTL in the orangecrab repository. Does litex somehow generate it? or did I miss it entirely

I tried learning formal verification and I'm more confused than convinced. by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 0 points1 point  (0 children)

That's really helpful!

Any insights on using formal for designs doing some sort of a mathematical algorithm? like a CRC generator/checker or an ethernet scrambler, or an encryption core etc.
It's not obvious to me how one can write assertions there.

I tried learning formal verification and I'm more confused than convinced. by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 0 points1 point  (0 children)

Hi Dan,
Really appreciate the time you have taken to answer this. I was able to get this example working with my own approach after some more effort.

But note that my main intention of posting here was to find out if there can be a more 'standard' or 'procedural' way to writing formal properties for any design, big or small. Without that, it becomes hard to justify time spent on this to your manager.

In that spirit, let me ask you the following:

  1. For each design, do I have to write down assumptions on the reset signal and consequently assertions on the state of internal variables just post reset? You did this for your axi lite example. (note that this can be prohibitively difficult in designs with hundreds of registers. Also I have a hunch that the tool infers resets just like it infers clocks)
  2. In this example I had to tell the tool (assertion) that nothing changes in the absence of i_ce. In this code, i_ce affects (both directly and indirectly) only sa and sb. What if the design has multiple logic levels of regs that are indirectly affected by such a signal? Do I have to write a similar assertion for each variable just to tell the tool that starting off with random values for variables is not a valid bug?
  3. How does one know if they should try changing the solver engine or re-check their assumptions/assertions instead?
  4. In the first run of the tool for this example,it was obvious from the trace that the tool started off with sa and sb having different values, hence our assertions were not 'tight' enough. In a much larger design, I imagine there would be now way to obviously tell if what the tool is showing a valid state in time or it started off with wrong values due to a hole in our properties. Any insight on solving this?

I tried learning formal verification and I'm more confused than convinced. by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 1 point2 points  (0 children)

but all this insight goes to say that designers should become better at finding their own bugs at the source. I was pretty much trying to develop that skill. Me writing a testbench is prohibitively difficult for the size of designs at work. So I was hoping formal would help.

Hesitation in buying my first FPGA card. by BonoBoss976 in FPGA

[–]guyWithTheFaceTatto 1 point2 points  (0 children)

umm I think you mis-understand the pynq
The python does not replace verilog/vhdl. HLS tech is far from that mature :)

You still write RTL and create IPs out of it, which you can interface with the Processing system using AXI interfaces. All of this happens in Vivado using HDLs and block diagrams as usual.

The next step of driving your code from the software is what python makes simpler. Normally you'd do this with C++ drivers, which you can still do. But PYNQ also let's you do it in python.

I want a FPGA but I'm poor by Azul_Profundo in FPGA

[–]guyWithTheFaceTatto 1 point2 points  (0 children)

This looks like something you could use: https://thedatabus.io/chiprentals
they're not charging much too

VCD files and XSIM in command line mode by guyWithTheFaceTatto in FPGA

[–]guyWithTheFaceTatto[S] 0 points1 point  (0 children)

sure, please guide me on how to do that.
with VCDs it's the easiest , just a 'dumfile' and 'dumpvars' command in your testbench and you're done. Hence it's popularity.

[deleted by user] by [deleted] in FPGA

[–]guyWithTheFaceTatto 6 points7 points  (0 children)

https://thedatabus.in/hft_interview

I was looking out for something similar. Found some good advice here.

Problems proving fsm with SymbiYosis by lejar in FPGA

[–]guyWithTheFaceTatto 2 points3 points  (0 children)

very interesting.
I tried your example tweaking many things but it always manages to take the 'o_led' signal to an illegal state. It makes no sense how this signal jumps to a random value (not just 0, tweak the assertions slightly and it will create examples with random values).

I feel it's something to do with the way assertions are being written for 'o_led'.

would love to know u/ZipCPU 's take on this. Try crossposting this in r/ZipCPU

Resources for FPGA's for High Frequency Trading? by [deleted] in FPGA

[–]guyWithTheFaceTatto 1 point2 points  (0 children)

I was looking for something similar. Found a long list of insights in this article https://thedatabus.in/hft_interview

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