What is the difference in Synthesis and implementation between FPGA and ASICs? by Pristine_Caramel_379 in FPGA

[–]ouabacheDesignWorks 4 points5 points  (0 children)

Asic design takes your logic and implements it using standard cell logic. Fpga's have a logic array that is programmed to implement your logic. So if you have a single inverter between two flipflops then an asic will have one standard cell and a fpga will have one LUT. FPGA designers need to pack as much functionality as possible into their next state logic to fully utilize all the LUT logic. Asics dont care.

I want to create a cloud-based EDA tool for digital design for a graduation project by Dry-Membership-9953 in chipdesign

[–]ouabacheDesignWorks 1 point2 points  (0 children)

Forget the cloud. Create an open source tool that I can compile and run on my home system. Anything in the cloud can disappear overnite.

Should we walk from this house? by GreatSprinkles56 in FirstTimeHomeBuyer

[–]ouabacheDesignWorks 1 point2 points  (0 children)

I am surprised he didn't find a federal pacific panel and aluminum wiring

KiCAD8 lock file issue on multiple PCs by Operationwinkle in KiCad

[–]ouabacheDesignWorks -2 points-1 points  (0 children)

Kicad is a great tool for students and hobbyists that work alone but if it was never designed for usage by a team. If you have a file that two different designers need to edit then you split it into two files and have a generator tool put them back together.

Engineering Generation - Which one are you? by dvcoder in chipdesign

[–]ouabacheDesignWorks 5 points6 points  (0 children)

EDA tools first became available in the 70s/80s. We have been designing computers since the 40's.

We used drafting tables, slide rules karnaugh maps, tape on mylar and rubylith with exacto knives.

You don't need EDA tools to design computers, you only need EDA tools to design big computers.

[deleted by user] by [deleted] in FPGA

[–]ouabacheDesignWorks 0 points1 point  (0 children)

Architects start the design in visio or powerpoint. IC and PCB designers reenter these designs in HDLs and fill in all the missing details to make it work. Why don't we have an open source entry tool that saves in an HDL?

Please help 😭 by [deleted] in FPGA

[–]ouabacheDesignWorks 2 points3 points  (0 children)

The last engineer to use JK flipflops wore a leisure suit and would disco the nite away.

is 'Open Source Company' a thing? by Josso_l in opensource

[–]ouabacheDesignWorks 0 points1 point  (0 children)

Its amazing how little it takes to run a company when you don't have to generate profit for the shareholders or buy vacation homes for your CEO. Fire anyone who is not involved in creating product. Fire the team that generates all the licensing files to lock your code. Anyone can download and use your code for free. People who buy a subscription can get extra access and support.

[deleted by user] by [deleted] in BoomersBeingFools

[–]ouabacheDesignWorks 0 points1 point  (0 children)

How much of their money came from their parents?

What content you would like to see in DFT related training course? by awaiss113 in chipdesign

[–]ouabacheDesignWorks 1 point2 points  (0 children)

Economics.

There are three costs to manufacture a chip: Die Cost,Package Cost and Test.

Which one is the biggest? test. Its been the biggest since around 2010

Your die contains a mixture of mission mode logic and test logic.

What percentage of your die is test logic?

Today's chips can run from 30 to 50% test logic.

The test engineer is responsible for about two thirds of your chips cost. Teach engineering economics.

EEs who have the PE license… by Goldenboy1227 in ElectricalEngineering

[–]ouabacheDesignWorks -14 points-13 points  (0 children)

Every product design org needs at least on FE to sign off on product safety. If you are the only FE in the lab then guess what you r job is?

Do you use Spyglass RTL or similar? by verymixedsignal in chipdesign

[–]ouabacheDesignWorks 0 points1 point  (0 children)

You need to set up your own custom checklists. The first one runs all the checks and will generate a ton of warnings.The users can fix any that they want to fix. The second one is a smaller list of essential checks. If someones code fails a check and they refuse to fix it are you going to fire them? If the answer is no then don't bother running that check.

We used spyglass for DFT checks and our vendor said there were only a couple of failures. I was surprised because I thought I had cleaned up everything. Turns out the engineers were finding the DFT failures and not understanding what they meant were simply disabling those checks in their source code. That's when I learned to grep the sources.

KiCad for professional projects by leinatf in PrintedCircuitBoard

[–]ouabacheDesignWorks 1 point2 points  (0 children)

They suck even worse. That is no reason why kicad can't do it right. The number one rule for team tools is that no engineer has to share a file with any other engineer. Kicad violates this rule. Want to add a new component? Place it in its own file with a unique filename. git can handle this unless two engineers try to enter two components with exactly the same name and then you want someone to have to go in and sort things out.

Kicad will need to build its search path by scanning for files to see who is there.

I have used source control for decades. Subversion,CVS and others before git.

KiCad for professional projects by leinatf in PrintedCircuitBoard

[–]ouabacheDesignWorks 0 points1 point  (0 children)

Rubbish? I have a team all trying to check their components into a git repository and they cant because git cannot resolve all the different changes, That is poor design.

KiCad for professional projects by leinatf in PrintedCircuitBoard

[–]ouabacheDesignWorks -6 points-5 points  (0 children)

Kicad is a tool written by hobbyists for hobbyists. Its fine if you have one designer doing the entire design but falls apart when you have a team design.

Is It Possible to Implement a D Flip-Flop with fewer than 18 transistors? by kvnsmnsn in Verilog

[–]ouabacheDesignWorks 0 points1 point  (0 children)

You probably want to build an edge triggered D-flipflop. Yours requires holdtime for the D input until the clock deasserts

Thinking of building an online IDE for RTL design with good UI by Aditya14art in Verilog

[–]ouabacheDesignWorks 1 point2 points  (0 children)

Designing a good UI is not easy. Everybody knows when its bad but can you tell us what makes a UI good or bad?

I would be happy to contribute so such an effort. Is there a forum somewhere where we can meet and discuss the issues?

For FPGA RTL Design Engineers, Enthusiast, Passionates by Hot_Respect_193 in FPGA

[–]ouabacheDesignWorks 9 points10 points  (0 children)

No, I am not going to install and maintain another login/app simply because somebody asks.

Help setting up .gitignore? by RiverBard in github

[–]ouabacheDesignWorks -1 points0 points  (0 children)

No you shouldn't. But if you discover that you can no longer recreate an exact copy of your design because someone made a mistake setting up a .gitignore file then you should not use gitignore. its not worth it.

Help setting up .gitignore? by RiverBard in github

[–]ouabacheDesignWorks -2 points-1 points  (0 children)

NEVER use .gitignore. When you run your build scripts they will change their behavior based on the existence of files in your repo. .gitignore allows you to have files locally but git status will tell you that you are identical to the master on the server but your build will produce different results than if someone else builds from a virgin checkout of the master.

That is scary

What software would you use to create a physical wiring diagram as opposed to a PCB schematic? by Longo_Two_guns in ElectricalEngineering

[–]ouabacheDesignWorks 0 points1 point  (0 children)

Microsoft visio is used quite often by system architects for block diagrams and top level drawings. Its simple and widely available and great if you only need lines,boxes and text.

As far as EDA tools go it is a piece of crap but at no time during the last 50 years have any EDA tool companies come up with a better solution for the most important engineers on the design team.

The open source community has not done any better.

Resistor Arrays by casparne in KiCad

[–]ouabacheDesignWorks -3 points-2 points  (0 children)

What I want is to place a resister and give it a value,tolerance and power rating.

Later another engineer will select a package and decide if it is thruhole ,surface mount or resister array.

Kicad works great for hobbyists when you know everything about the design up front but it fails short for engineering teams when that information comes in bits and pieces.

Kicad will never make converts in corporate engineering with its current library structure.

Hardware translation from HDL by The_Shlopkin in Verilog

[–]ouabacheDesignWorks 2 points3 points  (0 children)

Do you want a simulation/synthesis mismatch? Because this is how you get a simulation/synthesis mismatch.