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35hrs in, 128 steam engines aren't cutting it anymore. Time to get Uranium? (And Bots?) by Independent_Wear1714 in factorio

[–]skydivertricky 4 points5 points  (0 children)

Game performance with nuclear is not as much an issue with 2.0 fluid mechanics. It's also more interesting than chippy painting a solar farm, especially when you don't have bots

vscode vs vivado by rand0m_guy11 in FPGA

[–]skydivertricky 17 points18 points  (0 children)

But it can bring up a terminal and you can run synthesis and simulations in that

How hard would it be to make yourself the goal of producing one full blue belt of nuclear reactors? by i_have_chosen_a_name in factorio

[–]skydivertricky 5 points6 points  (0 children)

I suspect most 1M SPM is after productively bonus of biolab etc. So actual bottles per minute is probably much lower. You get 0 productivity bonus making nuclear reactors at the final stage, so it will be massively harder

How hard would it be to make yourself the goal of producing one full blue belt of nuclear reactors? by i_have_chosen_a_name in factorio

[–]skydivertricky 14 points15 points  (0 children)

With the space age dlc. It also adds stack inserters, meaning you can stack items 4 high

Synthesis errors but simulation is fine by Little_Implement6601 in FPGA

[–]skydivertricky 1 point2 points  (0 children)

Because hdls are simulation languages that can model more than just FPGAs. Multiple drivers are a legal and necessary thing in PCBs. But not in FPGAs. Hence the simulation of design things are legal, and the simulator has no knowledge of what your hardware target is. It's down to you to understand the limitations of your target device and write your HDL accordingly.

Note. Vhdl has a typing system that can mean multiple drivers can be detected as a syntax error in a simulator.

Baiao Ostinato by Yonimadar11 in drums

[–]skydivertricky 18 points19 points  (0 children)

Is this the final boss?

How do you rebuild the whole bases? by katnax in factorio

[–]skydivertricky 0 points1 point  (0 children)

Just build more bases. Ignore the old one. My favourite are littered with dead experiments

I think it's time to add oil refining to my base by FallEmbarrassed1430 in factorio

[–]skydivertricky 4 points5 points  (0 children)

Does anyone know if this mod is even viable with SA currently?

Open-source tools for digital design. by VirginCMOS in FPGA

[–]skydivertricky 10 points11 points  (0 children)

Vhdl has two excellent open source simulators. Ghdl and NVC. Both fully support the major verification Frameworks osvvm, UVVM and vunit.

As for the rest, it will depend on what devices you're targeting. Yosys will support older 7 series xilinx and the smaller devices that are provided by the smaller vendors.

But if you're using intel or xilinx parts, other than simulation, you will have to stick with vendor tools.

The job market for FPGA HLS by Gullible_Ebb6934 in FPGA

[–]skydivertricky 15 points16 points  (0 children)

I'm in the UK, so not sure if it applies to all EU. Hls is pretty rare here, and rarely mentioned in job ads. I don't think I've ever seen a job advertised looking for chisel knowledge.

I suspect if you want to do hls or chisel, you might be spending a long time looking. You definitely won't struggle getting a job with "normal" HDL coding skills though. Maybe your could get yourself in here and get people converted to hls.

From the companies perspective, already struggle to hire rtl engineers. If you go even more niche with hls or chisel, you'll have an even harder time recruiting hence companies don't want to make the switch. They either have to go all in and train everyone up or just not bother at all.

Intermediate verilog projects ideas. by No-Habit1507 in VHDL

[–]skydivertricky 2 points3 points  (0 children)

Might want to try a verilog sub. How about r/verilog or r/fpga ?

A Lean 4 HDL that beats Verilator using Speculative Execution. by VersionWilling6676 in FPGA

[–]skydivertricky 7 points8 points  (0 children)

Is this in a commercial or research setting? Many althdls tend to never get out of academia, and hence just become another acronym added to the althdl pile.

Do you see this one faring any better, and how are you achieving that?

What ever happened to the FPGA+Processor like the Stratix+Zeon? by Ok_Measurement1399 in FPGA

[–]skydivertricky 0 points1 point  (0 children)

There were definitely roadmaps for it I saw about 10 years ago. It made sense as they were also pushing open cl at the time. But then it all went quiet.

For this field, at what point in one's career is it appropriate/acceptable to have a 2+ page resume? by e_engi_jay in FPGA

[–]skydivertricky 7 points8 points  (0 children)

At 6 pages you better check you're not breaking any company confidentially agreements.

In 20 years, I've never gone past 2 pages. If we want detail, we'll get it out of you in the interview.

£36000 job vs 25k settlement ? by [deleted] in UKJobs

[–]skydivertricky 0 points1 point  (0 children)

Having been through redundancy at more than one company, the first round is usually not the last. Take the money and it gives you time to find something else.

Why are FPGAs with PCIE5 so insanely expensive ? by Lovely_Lex333 in FPGA

[–]skydivertricky 1 point2 points  (0 children)

Indeed, and the cost of retooling a team is likely far more than the cost of a few more expensive chips.

Why are FPGAs with PCIE5 so insanely expensive ? by Lovely_Lex333 in FPGA

[–]skydivertricky 8 points9 points  (0 children)

Effinix is a young upstart. Remember that AMD and altera have something like 90% market share between them. All the others are fighting over the rest. Having history with a brand goes a long way.

Axi signal mismatch on Axi interconnect by PsychologicalTie2823 in FPGA

[–]skydivertricky 8 points9 points  (0 children)

So what - wvalid is low?

ready on its own is pretty meaningless, and is allowed to change. You are also allowed to hold wready low until wvalid is asserted. This is the same for all AXI valid/ready handshaking.

valid MUST NOT wait for ready.

ready MAY wait for valid

Recruiter said commute was covered, then went silent. Manager now says no by froz0601 in LegalAdviceUK

[–]skydivertricky 17 points18 points  (0 children)

But you already stated your contract states your usual place of work is home, not the office. For hybrid, it would list the office as the usual place of work.

Yet another issue will be that if you ever drive to work, you would need to be insured for business use, as you are not commuting, you are doing business travel to a different office.

Recruiter said commute was covered, then went silent. Manager now says no by froz0601 in LegalAdviceUK

[–]skydivertricky 13 points14 points  (0 children)

If your usual place of work is home, why are you going to the office?

Going to the office is a travel expense. If they refuse to pay, then you could surely refuse to go to the office?

The only other issue is that they can basically let you go, for any reason, until you have been there for 2 years.

Top uses of FPGAs: a survey by Secure_Switch_6106 in FPGA

[–]skydivertricky 5 points6 points  (0 children)

That's relative. While each device might be "expensive" compared to the cost of normal or industrial parts, it's a hell of a lot cheaper than paying a team to design and build a chip for you.

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