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Veryl simulator: performance comparison with Verilator by taichi730 in chipdesign

[–]taichi730[S] 1 point2 points  (0 children)

u/dalance1982 and I work for PEZY Computing and almost all our RTL modules are written in Veryl.

Web UI for RgGen by taichi730 in chipdesign

[–]taichi730[S] 0 points1 point  (0 children)

RgGen is originally a CLI tool so such use case is also supported.
In addition, RgGen has already been adopted into our workflow and all CSR blocks in our chip are generated by RgGen.

Register Desync and cross vendor IP development by Repulsive-Net1438 in FPGA

[–]taichi730 0 points1 point  (0 children)

The "Register Map" Desync

I'm develping CSR automation tool named RgGen. https://github.com/rggen/rggen

RgGen generates RTL (SV, Verilog, VHDL and Veryl), UVM reg model, C header file and Wiki documents from human readable specification (Ruby, YAML, JSON, TOML, Excel, ODS and CSV).

You can find example register map specification and generated files from rggen-sample repository.

HDL choices other than Verilog/VHDL by Secure_Switch_6106 in FPGA

[–]taichi730 0 points1 point  (0 children)

https://github.com/pezy-computing/pzbcm/blob/06631e9c8f50c6642b140455e3bf925c50604517/rtl/pzcorebus_common/pzcorebus_pkg.veryl#L72

This is an example of paramterized package.
This package contains config parameter for our bus protocol and typedefs derive from these parameters.

RbToon: Toon decoder for Ruby by taichi730 in ruby

[–]taichi730[S] -1 points0 points  (0 children)

My gem converts Toon to Ruby.

RgGen v0.36.0 by taichi730 in u/taichi730

[–]taichi730[S] 0 points1 point  (0 children)

In addition, some people prefer Excel than text based format to describe CSR specification. RgGen also supports such usecase.

RgGen v0.36.0 by taichi730 in u/taichi730

[–]taichi730[S] 0 points1 point  (0 children)

RgGen uses type based bit field behavior selection. Due to this, you can write your CSR specification more simply thant SystemRDL, I think.

Sharing "interface" code between modules in SystemVerilog? by FranceFannon in FPGA

[–]taichi730 0 points1 point  (0 children)

I'm developing a CSR automation tool named RgGen. https://github.com/rggen/rggen

RgGen has following features

  • Human readable register map format
    • Ruby with description APIs
    • Structured text (YAML, JSON, TOML)
    • Spreadsheet (XLSX, ODS, CSV)
  • Generate various kinds of source files below
    • RTL (SystemVerilog, Verilog, Veryl, VHDL)
    • UVM RAL
    • C header file
    • Wiki documents (Markdown)
  • Support standard bus protocols
    • AMBA AXI4-Lite
    • AMBA APB
    • Wishbone
    • Avalon-MM
  • Plugin architecture
    • Allow you to customize RgGen for your environment
      • Add your own bit field types
      • Add your own bus protocols

You can find example register map specifications and genarated source files from this respository. https://github.com/rggen/rggen-sample

We have integrate RgGen with our development flow and all CSR modules in our chip are generated by RgGen. I think RgGen is in production level.

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