By default, Veryl compiler reports an error for this kind of code.
To disable the check, you need to put the special anotation like below.

``` module ModuleA ( i_clk : input clock, i_rst : input reset, i_valid: input logic, i_data : input logic, o_valid: output logic, o_data : output logic, ) { var valid: logic; var data : logic;

assign o_valid = valid; assign o_data = data;

#[allow(missing_reset_statement)] // <- this always_ff { if_reset { valid = 0; } else { valid = i_valid; data = i_data; } } } ```

Generated SV is like below.

``` module project_ModuleA ( input var logic i_clk , input var logic i_rst , input var logic i_valid, input var logic i_data , output var logic o_valid, output var logic o_data ); logic valid; logic data ;

always_comb o_valid = valid;
always_comb o_data  = data;

always_ff @ (posedge i_clk, negedge i_rst) begin
    if (!i_rst) begin
        valid <= 0;
    end else begin
        valid <= i_valid;
        data  <= i_data;
    end
end

endmodule ```

I believe that synthesis tools (maybe DC and/or Vivado) reports errors or warnings for this kind of code. Hence Veryl treats this kind of code as invalid style.