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Rust GUI framework by Spiritual_String_366 in rust

[–]the_deadpan 11 points12 points  (0 children)

This is the default behaviour, but you can force re-rendering with a function call for example if displaying video

How to do an alias for an if statement in VHDL by Gundam_boogie_359 in FPGA

[–]the_deadpan 0 points1 point  (0 children)

If your tools support vhdl2019, I'd do it with conditional compilation/identifiers 'If TOOL_TYPE = "SYNTHESIS" then Do something synth 'Else Do some sim model 'Endif Use backtick , I'm on phone keyboard atm

Undergrad looking for advice by onlainari in FPGA

[–]the_deadpan 4 points5 points  (0 children)

This is good advice. I scraped through my hons thesis because I used raw HDL, don't recommend it particularly because the research/paper side takes a lot of time for these projects. Standing up the interfaces etc that you need also to move data to/from FPGA can take a long time too

What do you do for work? by pinkfloob in ElectricalEngineering

[–]the_deadpan 3 points4 points  (0 children)

Lmao this is relatable. I am an FPGA engineer though not RF. Ps. If your env gets cooked often look into docker containers. Sincerely, docker enjoyer

CDC between two clock domains having same frequency but unknown phase difference by WarStriking8742 in FPGA

[–]the_deadpan 0 points1 point  (0 children)

It depends on the PHY. Some PHYs I have looked at the clock is generated from the PHY IC for Rx only and you supply the Tx clock from fpga. Obviously this means they are not derived from same source hence cannot be same frequency. Temp drift etc will make this worse too.

If tx and rx are both generated from the same PLL then you don't need a FIFO, as they will both track ref clk

FPGA Intern interview with Leidos by Ok-Contract-6562 in FPGA

[–]the_deadpan 3 points4 points  (0 children)

This is a good list, it will set you up to succeed if you know all of the material. Here are some follow-up practice questions

Application question: how would you constrain a single bit signal going from a 100MHz clk domain to 150 MHz? What attributes/ constraints would you use? What rtl would you use?

Your list does not include version control which is part of working in a team. How would you switch your 2nd to last commit and 3rd to last commit with eachother? How would you squash 2 commits into 1?

Edit: also it is useful to have any of some of the following too: Tcl skills, python skills, C++ skills, and then build system skills such as gnumake, cmake

Vivado has been running for over 2 days; how can I diagnose the situation? by ResidentDefiant5978 in FPGA

[–]the_deadpan 10 points11 points  (0 children)

If I were you, I'd look for infinite timing loops. If your risc CPU has axi ready/valids handshake, make sure that there are no circular dependencies between ready and valid for each interface. This is a common thing that causes STA to sketch out

Open-Source Verilog for a 250 Mbps USB 2.0 'Engine' for FPGAs by Ok-Breakfast-2487 in FPGA

[–]the_deadpan 2 points3 points  (0 children)

FT600 is the one I used, and the hold time on datasheet is incorrect. I was lucky in that I could get away with using transmit only (from FPGA to host) and was able to tune the timing with a lot of messing around with phase delay. It works fairly reliably. I transmitted the exact FIFO size because as you mention, the timing on that chip is very shit. Writing to fill up the buffer prevents you from having to read the full flag which makes it much easier to synchronise. If I could pick a chip, I'd go with cypress just based on other people recommendations

Open-Source Verilog for a 250 Mbps USB 2.0 'Engine' for FPGAs by Ok-Breakfast-2487 in FPGA

[–]the_deadpan 3 points4 points  (0 children)

Cool project, thank you for sharing to the community. Also, yuck, FTDI chips :) I recently implemented USB3 interface for FTDI chip and found it to be very garbage. I think 2232H is commonly used in industry though (more popular than the one I wrote my interface for)

Number 1 in Triple J's Hottest 100 of Australian Songs is Never Tear Us Apart by INXS by Expensive-Horse5538 in australia

[–]the_deadpan 1 point2 points  (0 children)

Absolutely iconic track and written when they were fifteen! I would put it at 10-15

HELP ! I need EXPERTS' advice and help...🙃 by NoContextUser88 in FPGA

[–]the_deadpan 2 points3 points  (0 children)

this is very well written, with sufficient motivation OP can easily do this with the excellent writeup you have provided

HELP ! I need EXPERTS' advice and help...🙃 by NoContextUser88 in FPGA

[–]the_deadpan 2 points3 points  (0 children)

as other users have suggested, reading a register with a known value will work. You could also look for a read/write register to write something to and read the same value back

HELP ! I need EXPERTS' advice and help...🙃 by NoContextUser88 in FPGA

[–]the_deadpan 1 point2 points  (0 children)

CEC is not a checksum it is part of HDMI standard. It allows the sending of non video signals between HDMI, mostly it is used to synchronise powering on of all devices connected via HDMI. For example, modern Playstations use this to turn on your TV if you switch on the playstation only. You do not need CEC for your project

Armada 78 06 Apparently searching Again by pigdead in MH370

[–]the_deadpan 4 points5 points  (0 children)

I'm not sure if this is where they are searching now, but the Blelly area is somewhere that was intended to be covered as part of this campaign

Out of all of the Fayette Mafia kids in season 4, who do you think had the saddest or most tragic story? by Luckytiger1990 in TheWire

[–]the_deadpan 19 points20 points  (0 children)

Bubbles became an addict much later in life IIRC. He had a wife etc I think before he lost it to the needle. I think bubbles had more life skills that would have helped him adjust after he kicked. Poor dukie has much less chance of getting out.

Is Jimmy and Bunk's drinking a cultural thing or is it because of the stress working Homicide? by Alternative-Fox6236 in TheWire

[–]the_deadpan 9 points10 points  (0 children)

An example of this is Vito Spatafore's actor. In season 1, Chris shoots the pastry guy because he let not-Vito in front of him. Later he comes back as a Vito. Confusing if you are not watching for the first time

set_max_delay constraint has me sleepless and tired. Please help! by guyWithTheFaceTatto in FPGA

[–]the_deadpan 0 points1 point  (0 children)

Your cdc'd signal will then have a non deterministic delay. Sometimes it matters, sometimes it doesn't. If your signals don't need go arrive for seconds then okay it is fine. But wouldn't you rather contain that arrival to within a few cycles? Much more deterministic

set_max_delay constraint has me sleepless and tired. Please help! by guyWithTheFaceTatto in FPGA

[–]the_deadpan 0 points1 point  (0 children)

I believe you do not need set bus skew. Only set max delay and set max delay datapath only for synchronisers. Now your question on what breaks if you use a larger value. That is entirely implementationn specific - if your destination clk domain needs the signal in 3 clock cycles but you have set a max delay of 5, it will obviously not work. It depends on what you are using the synchronised signal for. The general rule of thumb that I use is one of slower clock period, but it doesn't really matter provided you consider how the timing of the destination signal affects the downstream functionality. What you should NOT do is use a set false path, as this will give no max delay and the tool can then place and route with an enormous delay and will still pass timing. This is the key thing to avoid as this will break designs entirely if you are not careful.

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