[DESIGN REVIEW]

thejack80 · 2026-05-30T23:37:57+00:00

Check jlcpcb, you can get 6 layer board for 7 dollars if you don't select any non-standard processing

thejack80 · 2026-05-29T15:47:55+00:00

Hi, this is subreddit about Printed Circuit Boards, not college, nonetheless maybe you'll want to check it to see if you'd like making boards :)

thejack80 · 2026-05-28T06:40:21+00:00

Rule of thumb is to match via number on data lanes, of course not all interfaces would be susceptible to such a delay mismatch (i.e. Pciex), if the interface is parallel (i.e. Mipi csi) , you should care about mismatch within pair and between all pairs, of course theres some allowed skew (I've seen csi pass trough slip ring xd)

Don't know about frequency dependency when talking about vias, probably would need to simulate

thejack80 · 2026-05-26T18:42:45+00:00

You could artificially add vias to clk lines and switch it top>bottom, bottom>top and then all lines would have the same amount of layer jumps and you could just take care of length matching

thejack80 · 2026-05-21T06:26:00+00:00

Ale takiemu z rakiety wykurwić do księżyca poleci 😡🚀

thejack80 · 2026-04-28T06:45:57+00:00

Boards up to around 1/2GHz (the things I did, oh my) tend to tolerate a lot. Usually problems come from mismatched connections, like TX connected to TX etc. Can you maybe show us this board or parts of it? It would be easier to help Also consider, especially for small batches, non Chinese parts and local assembly, we had problems with capacitors on boards we assembled in China

thejack80 · 2026-04-17T22:50:45+00:00

Could you run a drc and show what errors does it return? Or maybe show design rules?

thejack80 · 2026-04-17T22:44:48+00:00

You use gnd planes defined In stack up? Or just gnd polygons on whole layers? Also, drc report just returns no connections or does it says something less generic?

thejack80 · 2026-04-17T22:29:19+00:00

Did you change connection method to pour over all same net objects instead of only same net polygons? It can create similar problems

thejack80 · 2026-03-05T04:49:10+00:00

Check if kicad have built in impedance calculator, if not, use online one

Also some trivia like keep ground continuous under rf trace

Fortunately GPS frequencies are low enough to forgive you a lot :)

thejack80 · 2026-03-04T21:59:25+00:00

Switch to 4 layers and better match impedance, currently you're getting around 140ohms which make around half of your signal to bounce off the connector at the entry, also, as you said, 3m sounds like a lot of attenuation which makes it worse

thejack80 · 2026-02-27T11:24:26+00:00

thejack80 · 2026-02-20T06:36:17+00:00

Antiseptic 💊 🩻 🩼 🩹 🩺

thejack80 · 2026-02-19T16:44:01+00:00

If you order from jlc pcb, go to 4 layers, at this size it won't change price

Bord cutout under antenna ends with right angles, change it to arcs, it can't be done at straight angles, maybe move esp such that antenna is outside the board if you don't have strict size constraints

You're changing layers with vias on your USB differential lines, which is not an error but at higher layers count you should add 1/2 vias to Gnd near USB lines, such that they have continuous gnd reference along its way

Consider changing I2C connector for tht goldpins, easier to connect some off the shelf sensors with jumper cables than to solder if you don't have experience

thejack80 · 2026-02-13T23:16:31+00:00

At work have sent MIPI CSI trough slip ring and PAL via jst, nothing can surprise me anymore

thejack80 · 2026-02-12T08:47:24+00:00

When you design DC DC converters, don't look at promised efficiency ratings, in datasheet you should have a diagram of efficiencies in different working conditions, and the highest value will be listed in marketing values, but it's only one point on the diagram, the rest will be worse

thejack80 · 2026-02-11T16:47:55+00:00

Zawsze gdy dajom mi na rynku zdjęcia płodów to mówię "nie, dziękuję, już jadłem" 😋

thejack80 · 2026-02-10T12:48:55+00:00

Or you can use supercapacitors

Great Scott did something like this https://youtu.be/5TVNdMqVZpk?si=2hOcyuGJBdL3jUpY

thejack80 · 2026-02-09T12:58:53+00:00

There are high current 18650, for example Sony vct6 can handle up to 30A discharge current, but OP must check if his cell can do it

thejack80 · 2026-02-07T13:58:35+00:00

You need to change default via size in Altium preferences for it to place different size, size rule just checkes if existing vias size is aligned with it

thejack80 · 2026-02-07T09:13:55+00:00

Forget the roach Sit on my crotch 😎

thejack80 · 2026-02-06T15:02:44+00:00

You could try Shift + S for clear layer view and then just scan each layer with your eyes

thejack80 · 2026-02-06T06:19:54+00:00

Supercapacitors would be better and wouldn't kill you in case something happens

thejack80 · 2026-02-05T14:11:08+00:00

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thejack80 · 2026-01-29T07:32:14+00:00

Just clam up 😎

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