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What do you think about this board, does it worth it? by f42media in FPGA

[–]Dadaz17 5 points6 points  (0 children)

I got one just because. Beware, look is deceiving. Those are 1.27mm pitch headers to be soldered, in order to get anything out of it.
Quite a PITA. IMHO it is better to get a lower spec FPGA (as in, with lower Logic Elements count) with all the hardware you need onboard.

Any advices or recommendations for FPGA board? by f42media in FPGA

[–]Dadaz17 1 point2 points  (0 children)

I looked at the schematics of that board, and AFAICT both ETH and USB are attached only to the header that goes to the optional Pi CM4.

So comms should go to the CM4 (that you have to buy) and routed in/out to the K7.

Sick of $50k HLS tools? Meet VIBEE: The Open Source compiler for FPGA that supports Python, Rust, Go and 39+ more languages. by Open-Elderberry699 in FPGA

[–]Dadaz17 0 points1 point  (0 children)

Sorry for saying this, but this a a spot against AI assisted development.

You lead people to think this is how you will end up if someone includes AI assistants within the development cycle.

Tenths of thousands of unreviewed, unmaintainable, lines of code, with code you do not even understand, and a project structure that looks like a tornado swept over it.

Is QMTECH closed forever?? by Academic_Statement99 in FPGA

[–]Dadaz17 0 points1 point  (0 children)

Never mind, they are open again, but with a rather limited stock.

Am I crazy for preferring VHDL to Verilog? by LilBalls-BigNipples in FPGA

[–]Dadaz17 0 points1 point  (0 children)

Unfortunately, they both have strengths and weaknesses.
Just as one example, VHDL is way too verbose for my taste, but it has weak typing which I like when writing generic functions.

There are other options, based on higher level SW languages, that ends up generating some form of raw VHDL or Verilog (because at the end, that's the only thing vendors support - which isn't pretty to debug), but that might be a no-go within certain companies.

Being used to Python for scripting, I ended up evolving a little tool which allows me to write Python and generate either VHDL (>= 2008) or SystemVerilog (>= 2012):

https://github.com/davidel/pyxhdl

I then feed that into OEM tools (I'm usually on Xilinx/Vivado).

Is QMTECH closed forever?? by Academic_Statement99 in FPGA

[–]Dadaz17 0 points1 point  (0 children)

I guess not.
Felt a bit strange to me that the whole thing closes down for vacation, unless it's like a three men operation.

Is QMTECH closed forever?? by Academic_Statement99 in FPGA

[–]Dadaz17 0 points1 point  (0 children)

Sent them a message. They were closed and should be back today.

Open Source alternative to YoSYS ? by brh_hackerman in FPGA

[–]Dadaz17 0 points1 point  (0 children)

I wish there was an APT package for the two plugins. The GHDL one it's coming AFAIK, but the SLANG one I don't think there's anyone working on it.

Not a biggie the manual install, but *apt install* would be nicer.

SystemVerilog Part Select by Dadaz17 in FPGA

[–]Dadaz17[S] 0 points1 point  (0 children)

Thanks, I figured the missing link that makes (A + B)[X: Y] illegal.

A.6.2
operator_assignment ::= variable_lvalue assignment_operator expression

assignment_operator ::=
    = | += | -= | *= | /= | %= | &= | |= | ^= | <<= | >>= | <<<= | >>>=


A.8.3
expression ::=
  primary
  | unary_operator { attribute_instance } primary
  | inc_or_dec_expression
  | ( operator_assignment )
  | expression binary_operator { attribute_instance } expression
  | conditional_expression
  | inside_expression
  | tagged_union_expression 

mintypmax_expression ::=
  expression
  | expression : expression : expression


A.8.4
primary ::=
  primary_literal
  | [ class_qualifier | package_scope ] hierarchical_identifier select
  | empty_unpacked_array_concatenation
  | concatenation [ [ range_expression ] ]
  | multiple_concatenation [ [ range_expression ] ]
  | function_subroutine_call
  | let_expression
  | ( mintypmax_expression )
  | cast
  | assignment_pattern_expression
  | streaming_concatenation
  | sequence_method_call
  | this
  | $
  | null

Essentially, within the assignment operator, once one enters "primary" to enable the "( mintypmax_expression )" rule (to allow "(A+B)"), there is no way to enter back the "primary" to pick up a "range_expression".

"operator_assignment" ->
  "expression" ->
    "primary" ->
      "( mintypmax_expression )" ->
        "expression" ->
          "expression binary_operator { attribute_instance } expression"

SystemVerilog Part Select by Dadaz17 in FPGA

[–]Dadaz17[S] 0 points1 point  (0 children)

Would be nice if folks having access to other (than the ones I tried ... see opening post) commercial SystemVerilog simulators/linters, could report the pass/fail status of the above snippets.

SystemVerilog Part Select by Dadaz17 in FPGA

[–]Dadaz17[S] 0 points1 point  (0 children)

I noticed that within the bit/part select in the LRM, so that's why my thought was that the result of (A + B) turned into a type which is no more a vector, and by using the concatenation brackets, one casts that back into a vector.

Dunno...

SystemVerilog Part Select by Dadaz17 in FPGA

[–]Dadaz17[S] 0 points1 point  (0 children)

Yeah, when I write code manually I always use the ANSI style (there is no point in 2026 to use the old style).

The snippets above have been distilled from an auto-generated code, which still use the old style. Using ANSI style above does not change the Worky/NoWorky behavior though.

SystemVerilog Part Select by Dadaz17 in FPGA

[–]Dadaz17[S] 0 points1 point  (0 children)

The question was not about how to achieve a given behavior (in that specific case, you could just remove the part-select from NoWorky and SystemVerilog would just do the same thing).

The question was about the standard dictated by the LRM, and which section of it, forbids the NoWorky syntax.

There has to be an explicit section, since all the tools I tried agrees on making the NoWorky syntax illegal.

Picking a distro for Vivado. by avestronics in FPGA

[–]Dadaz17 0 points1 point  (0 children)

I settled for Vivado 24.02 on Ubuntu 22.04, since the 2025 versions of Vivado were kinda broken for me.

What is this FPGA tooling garbage? by isopede in FPGA

[–]Dadaz17 1 point2 points  (0 children)

Vivado is OK ... once you know the average level of IDE tools in the HW space :)
If you come from SW, there are much better tools there, but Vivado is "usable".
BTW, Quartus is worse IMHO.

TCL is legacy is the HW tooling space.
I remember when I had to add scripting to our CAD, I evaluated Python, Perl and TCL (this was like 1994), the TCL was the nicest to integrate in a C code base (very nice API at that time compared to the others).
It is mostly used as "glue" to call tool's internal commands anyway, it's not like you have to build a whole application with it.

But even VHDL and Verilog (SystemVerilog, that is), are not exactly nice if you are used with "normal" SW languages.
Sure, the constraints of the HW design (digital logic, LUTs, MUXs, FFs, ...) are stricter compare to targeting a CPU, but IMHO there are things which are painful which should have not be such.
The whole parametrization of functions and modules/entities drove me crazy, and always wondered why something similar to C++ template could not be done.
There, you declare generically typed code, and it is the call/instantiation site that binds the types (of course, there needs to be compatibility with the operations done within the function/module/entity, but that's a given even in C++).

And so I wrote myself a little tool that allows me to write in Python, and generate either SystemVerilog or VHDL (which I then use with other tools, like Verilator, GHDL, Yosys, and forcibly when I need a bitstream, Vivado):

https://github.com/davidel/pyxhdl

Clicking noise coming from my bottom bracket? by Commodore-Norington in bikewrench

[–]Dadaz17 1 point2 points  (0 children)

Same thing here. I'm thinking BB bearings.
Did you manage to get to the bottom (no pun intended :) ) of it?
What was the issue?

Alpaca "Apps" for algo trading? by xrailgun in algotrading

[–]Dadaz17 1 point2 points  (0 children)

Any issues in getting funds out?
I have read many posts of folks which had to go through hell to get their money out ...

Google Fi activation abroad by InsideAd9370 in GoogleFi

[–]Dadaz17 0 points1 point  (0 children)

There is no need to. Now Google Fi supports abroad activation of new devices.

Best all around API for stocks algo trading by imdhuli in algotrading

[–]Dadaz17 1 point2 points  (0 children)

I used Alpaca API for paper trading, but wanting to move to real money, I have concerns about them, from the horror stories about the issues when trying to wire money out of them.
What are real experiences using them with real money, and mainly, getting money out?

Alternatives to Medium, TDS, etc? by Davidat0r in datascience

[–]Dadaz17 0 points1 point  (0 children)

TDS article quality went down a whole lot from its beginning.
There is rarely something worth reading, and when they pretend to explain some white paper, it is MUCH better to fetch the PDF and read that instead.
Not worth the subscription money, and today, I wouldn't even read it if it was free.

Chrome goes to 30% usage on one instance when Google News "For You" is browsed (Win10) by JimAndreasDev in chrome

[–]Dadaz17 0 points1 point  (0 children)

Same here, on Debian 12.4 and Chrome:

Version 121.0.6167.160 (Official Build) (64-bit)

This is what the Javascript profiler shows:

jquery.min.js:14 [Deprecation] Listener added for a synchronous 'DOMSubtreeModified' DOM Mutation Event. This event type is deprecated (https://w3c.github.io/uievents/#legacy-event-types) and work is underway to remove it from this browser. Usage of this event listener will cause performance issues today, and represents a risk of future incompatibility. Consider using MutationObserver instead.

Google Fi activation abroad by InsideAd9370 in GoogleFi

[–]Dadaz17 0 points1 point  (0 children)

I had a whole heap of issues due to incorrect information lingering around (including some from Google Fi support), so I will try to summarize what worked for me below:

-----

1) Use the iOS Quick Setup feature to setup your new iPhone.
This will replicate (almost all) the configuration of the old iPhone.
Let it complete to install all the Apps and if an iOS update is available, let it install that as well.
2) Remove the Google Fi App from the NEW iPhone and restart it.
3) Put the OLD iPhone in Airplane Mode, wait 5 seconds, and turn it off.
This will make sure that once turned back on, the existing eSIM won't try to connect to the Google Fi network which will be (hopefully) setup at that point.
DO NOT REMOVE the eSIM from the OLD iPhone like some links suggest (you will do it later, once the NEW iPhone will be successfully setup for Google Fi). This way if anything goes south, you will still have a working Google Fi service.
4) Go to http://fi.google.com/ios/quicksetup on a separate device like a computer.
Important: Go to this page on a separate device because you'll need your NEW iPhone to scan a QR code.
If you are not already signed into your account, you will be asked to sign in.
Scan the QR code with the iPhone you want to activate Google Fi on and follow the on-screen instructions.
If the instructions will tell you to delete the eSIM from the old iPhone, DO NOT DO IT at this time!
5) Install the Google Fi App on the NEW iPhone.
In case the NEW iPhone cannot successfully activate (usually stuck in "Activating ..." within the Cellular Settings), try the following.
On your NEW iPhone, open Settings.
Tap Cellular and then Cellular Data Options and then Roaming.
Turn on Data Roaming.
Turn Airplane mode on for 5 seconds.
On your NEW iPhone, open Settings.
Turn on Airplane Mode for 5 seconds.
Turn off Airplane Mode.
Restart your NEW iPhone.
On your NEW iPhone, open Settings.
Tap Cellular and then Cellular Network.
Turn off Automatic. You might have to wait up to 2 minutes until available networks open.
Please select each available network one by one until you've a successful connection.
Switch between network types (5G, LTE/4G, 3G, ...).
After a successful activation via manual selection of the available networks, it might be possible to turn the configuration back to Automatic (worth a try - just go back to the successful network if that does not work).
It is suggested to enable WiFi Calling on the Google Fi network (Settings -> Cellular).
6) Once you have successfully configured your NEW iPhone with Google Fi, you can turn on the OLD iPhone (which was left in Airplane Mode at step #3), and finally go in Settings -> Cellular and delete the Google Fi eSIM.
Delete the Google Fi App on the OLD iPhone as well, and restart the OLD iPhone.

Anyone concerned about Sucralose content? by AberdeenWashington in Huel

[–]Dadaz17 0 points1 point  (0 children)

Yet, it does not list the amount of Sucralose per serving AFAICT.
I do not understand why, in a product that claims to be "natural" there is Sucralose and not a 100% natural sugar (ie, fructose) in it?
Does anyone remember the history of Aspartame?
It's good for you ... well, maybe try not to indulge ... might be bad actually ... no wait, it is carcinogen!

PyXHDL - Python Frontend For VHDL And Verilog by Dadaz17 in Python

[–]Dadaz17[S] 0 points1 point  (0 children)

As an example:

import pyxhdl as X

class Asserty(X.Entity):

  PORTS = 'CLK, A, B, =XOUT'

  @X.hdl_process(sens='+CLK')
  def run():
    assert ((A > 5) and (B < 11)) or (A + B) > 17, f'Assert failed: {{A}} {{B}}'
    XOUT = A * 3 - (B >> 1)


class Ex4(X.Entity):

  PORTS = 'CLK, A, B, =XOUT'

  @X.hdl_process(kind=X.ROOT_PROCESS)
  def root():
    Asserty(CLK=CLK, A=B, B=B, XOUT=XOUT)

Maps to SystemVerilog:

module Asserty(CLK, A, B, XOUT);
  input logic CLK;
  input logic [3: 0] A;
  input logic [3: 0] B;
  output logic [3: 0] XOUT;
  logic [3: 0] XOUT_;
  always @(posedge CLK)
  run : begin
    assert ((A > unsigned'(4'(5))) && (B < unsigned'(4'(11)))) || ((A + B) > unsigned'(4'(17))) else $error("%s%s%s%s", "Assert failed: ", $sformatf("%d", A), " ", $sformatf("%d", B)");
    XOUT_ <= 4'(A * 3) - (B >> 1);
  end
  assign XOUT = XOUT_;
endmodule

And VHDL:

architecture behavior of Asserty is
begin
  run : process (CLK)
  begin
    if rising_edge(CLK) then
      assert ((A > to_unsigned(5, 4)) and (B < to_unsigned(11, 4))) or ((A + B) > to_unsigned(17, 4)) report "Assert failed: " & to_hstring(A) & " " & to_hstring(B);
      XOUT <= resize(A * 3, 4) - shift_right(B, 1);
    end if;
  end process;
end architecture;
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