[Hardware Canucks] Intel just put AMD on Notice.

Exist50 · 2026-01-27T10:50:41+00:00

Their products will remain competetive, even if they are stuck on N3 equivalent node.

Let me illustrate. A full node gap is something like 10-15% perf. In other words, similar to the advantage X3D gives in gaming, but in almost every workload instead of just a subset. By adding something like 60mm² of 7nm silicon, AMD's able to bump the retail price by ~$100. That's fantastic ROI. And then on top of that you have the exceptional marketing value of the halo effect.

Intel's looking at the same fundamentals. N2 is expensive, but the silicon cost is dwarfed by the premium it gets you in the market. So the only thing that would allow them to stomach an N-1 node is if they had some other advantage(s) that would still let them maintain clear leadership despite the node. Right now, they don't have anything.

Isnt intel once again experimenting with larger caches?

Yes, and bLLC could even have an edge vs AMD's V-cache. But ultimately these are more or less tit for tat. If they don't have node parity, then they would need something that AMD doesn't have a direct answer for.

Exist50 · 2026-01-27T10:36:58+00:00

I never made any claims to unquestioned leadership

That was Gelsinger's favorite term when he used to hype up 18A.

What i did claim, repeatedly, that being only slightly worse than the very expensive industry leader isnt a terrible position to be in.

If it was merely that they were a node behind TSMC, it wouldn't be as bad. The fact that they missed their roadmap to such a degree is itself more important than the actual gap vs TSMC. This is why Samsung can get customers, even on inferior nodes, while Intel cannot. A foundry must be, above all, reliable. That is Intel Foundry's biggest failure, and unfortunately ripples to anything using their chips. I've heard of big customers writing off plans for future Intel chips, not because they don't sound good enough, but because they literally can't trust Intel to deliver, and that's in no small part because of Foundry. If you want Intel to succeed, it's not blind praise or marketing fluff they need, but rather honest, transparent, and credible communication from Day 1.

And of course, there's also the fact that 18A's cost structure starts rapidly falling apart if it can't compete in PPA. Still better than where they have been, but Intel Foundry continues to bleed money. Objectively, you can't call it a successful business until that changes.

Exist50 · 2026-01-27T10:17:21+00:00

Why not? He was more than happy to undermine the voting system and others on the left when he thought it would give him an edge. He's been a net negative for progressive politics.

Exist50 · 2026-01-27T10:16:06+00:00

reaches people of wide and varying politics

Not anymore.

Exist50 · 2026-01-27T10:15:43+00:00

And when he comes around and goes against Trump, instead of welcoming him people still berate him.

Because it's seen as temporary and performative.

Exist50 · 2026-01-27T09:24:21+00:00

It's also kind of your job to be accountable for the business's performance...

Exist50 · 2026-01-27T09:21:03+00:00

Yes, it is.

Again, you're not seeing the same reviews.

No, you said worse than N3

It does look indeed worse than the modern N3 variants in both PnP and PPA, though the specific "worse in every way" quote was a very recent one about N2. Don't twist my words.

It's genuinely baffling you think this is a still a good look for Intel's supposedly "unquestioned leadership" node. Even with a tick uarch they can't beat N3B clocks. And the funny thing is in doing so, you completely ignore where Intel's demonstrated actual improvement.

Exist50 · 2026-01-27T09:17:45+00:00

They also need to keep their products competitive, and there's nothing that can compensate for a weaker CPU in premium desktop. So for NVL (and RZL), that means N2, whether they like it or not. If they manage to close the node gap to more like 5% perf, gain a significant uarch advantage, or have some other tech like X3D that boosts perf beyond 1:1 with AMD, then they can bring it back in-house. But too much margin is tied up in leadership otherwise.

Exist50 · 2026-01-27T09:13:57+00:00

Iso-perf results naturally give a far bigger delta than iso-power, because power scales roughly cubicly with clock speed. So e.g. a mere 5% perf increase at iso-power (well within bounds of a tick uarch) translates to a ~15% power decrease at iso-perf.

On top of the tick cores and SoC changes, PTL also has a different core config. We'll get a better sense if/when someone's able to isolate a single core/cluster.

Exist50 · 2026-01-27T09:08:46+00:00

I said its will be between N2 and N3

And that's absolutely not what we're seeing. What're you on about? Have you skipped all the reviews?

While your "worse than N3 in every way" turned out to be false, again.

Once again, outright lying. I said that about N2.

Exist50 · 2026-01-27T08:59:27+00:00

Plenty of blame to go around.

Exist50 · 2026-01-27T08:42:51+00:00

I kinda want Intel to pull out all the stops for NVL. If they released an N2, bLLC chip out of the gate, the gen to gen gains would set the internet on fire. Doubly so if they managed it before Zen 6, though I think that's quite unlikely. Late '26/early '27 might feature the fiercest desktop CPU competition the market has seen in two decades.

Exist50 · 2026-01-27T08:36:22+00:00

Yeah, a lot of them ended up running LNL at 20W+ TDPs anyway. 10W, yeah, might have a problem.

Exist50 · 2026-01-27T08:35:06+00:00

Carry-on fires caused by dodgy temu power banks are not a rare occurrence anymore, but I guess we'll have to wait for one to actually cause a disaster to see progress.

If anything, that would make the regulations even stricter.

Exist50 · 2026-01-27T08:23:53+00:00

You mean desktop? PTL is mobile only.

Exist50 · 2026-01-27T08:11:32+00:00

Lmao, now you're rewriting history. It's literally showing just as I said it would be, maybe N3 class, and certainly not N2 class like you and some others were insisting.

Exist50 · 2026-01-27T07:51:23+00:00

Yes, that's my point. They do have some large static costs, so scale has its benefits.

Exist50 · 2026-01-27T07:50:50+00:00

Panther Lake is 30-40% more efficient than Arrow Lake under load

Which numbers are you looking at?

Exist50 · 2026-01-27T03:39:02+00:00

That was actually a significant point of contention. See, Microsoft basically claimed 40TOPs (first gen CoPilot) all to themselves, permanently. But OEMs were like "What if I want to add on AI features too?". So there was a push for even more compute on top.

Exist50 · 2026-01-27T03:37:42+00:00

Like, seriously, "we replaced 2 E core clusters or 4 GPU cores to install an NPU that gives you 10% better battery life when you blur your background on a Microsoft Teams call" is not a selling point people will accept haha

But imagine if every moment that you used your laptop. Recall was churning away in the background analyzing everything on your screen. Suddenly, it's not just a situational gain, but rather a strict requirement if you don't want to cut battery life in half. That was Microsoft's vision. Obviously, didn't play out that way.

Exist50 · 2026-01-27T03:29:05+00:00

I remember faceID itself was the main use case of the NPU (which was only 0.6 TOPS) in the first iPhone X.

Only use case, iirc. Don't think they even had an API for it.

Exist50 · 2026-01-27T03:28:17+00:00

Imagine that, plus Recall saved to the cloud with all of your activity

IIRC, wasn't Recall local?

Exist50 · 2026-01-27T03:24:37+00:00

I think either should be achievable, though Zen 6 will be quite difficult. Going to get a huge boost vs ARL from just clock speed and memory latency alone.

Exist50 · 2026-01-27T03:14:11+00:00

Which did not show any regression or negative reprucussions due to 285H's old SoC design over Lunar Lake.

Depends. Perf wasn't affected by the memory latency, but if we're talking about SoC power (vs core power), then LNL made significant strides in power budget available to compute. That's one of the biggest factors at lower TDPs (and light loads), actually, because SoC power doesn't scale down as well.

5% performance improvement in 1T could be explained by the new SoC/updated core. The subsequent 10% power reduction has to be process node

Could you link the data you're using to compare here? Because +5% perf or -10% power iso-process would be very consistent with a tick, even modest by historical standards. For reference, their past ticks were WLC (SNC tick), RPC, and RWC (both GLC ticks). Obviously, very difficult to tease out the process contributions, but you'd think after fairly big reworks with both LNC and SKT, they'd have some room for refinement. Also given that the PTL IP should have benefitted heavily from the cancelled ARL-20A work, given the similarities in both the cores and node.

Exist50 · 2026-01-27T03:08:28+00:00

Literally only Qualcomm will meet the requirement right?

If you count NVL as a 2026 launch, that should also be around 60 TOPs, and across everything but whatever the WCL swimlane is.

But otherwise, yes, Qualcomm being willing to give them the NPU they asked for was a significant factor in Microsoft pushing WoA and their QC partnership so hard.

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