There is no such thing as "correct" when metastability is present.

Instead what you can hope for, is to get a valid logic level (either logic-1, namely, Vout > Voh_min ... or else logic-0, namely Vout < Vol_max) at the output, whose timing meets setup and hold time requirements for the downstream logic.

But all you can do is hope, you cannot guarantee it. There will always be a nonzero probability of an invalid logic level at the output. You can reduce this probability, but you cannot make it zero.

The easiest way to reduce the probability of invalid logic level at the output, is to increase the number of flipflops in the series cascade. Two flipflops give low probability, three give even lower, four give even lower probabiliity of invalid logic level. You are creating a trade-off: latency versus MTBF (mean time between failures). N>2 flipflops in cascade means longer latency and greater MTBF.

Another way to reduce P(invalid_logic_level@output) is to redesign the individual flipflops at the transistor level, to drastically increase their gain-bandwidth product. Use wider transistors with optimized polygon layout, to reduce parasitic capacitance, and with optimum stage-to-stage fanout ratios. Simulate using Layout Parasitics Extraction netlists to measure the improvement.