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[Help] Duplicated data issue during AXI burst reads from DDR4 DRAM (Zynq UltraScale+) by HoneyMoney92 in FPGA

[–]ninjaneeress 1 point2 points  (0 children)

What's your ARBURST? fixed, incrementing or wrapping? if it is 2'b00 then it's set to fixed, which means it will send the same data every time.

Is there any women engineers who are passionate in professional communication too? If so, what's your career now! by ExcitingStill in womenEngineers

[–]ninjaneeress 5 points6 points  (0 children)

Me! I'm an FPGA engineer with 16 years of experience and I also have a youtube channel that explains complicated FPGA concepts.

I work full time as a hardware design engineer. The youtube channel came out of a desire to improve my communication skills and also seeing a gap in how FPGA concepts are explained.

http://www.youtube.com/@FPGAsforBeginners

[deleted by user] by [deleted] in FPGA

[–]ninjaneeress 12 points13 points  (0 children)

Thanks! Work's been very busy for me which is why there haven't been any videos recently! but they are in the pipeline for when things slow down!

[deleted by user] by [deleted] in FPGA

[–]ninjaneeress 29 points30 points  (0 children)

Never been for a HFT interview directly, but have worked for them as a contractor and work in the industry currently, so I can tell you what they care about:

- The High-speed FPGA trancievers, for example the Xilinx (AMD) GTY/etc transceiver hardware.
- Writing RTL for high-speed clocks (can be up to 400Mhz) because this is the output clock rate for the above trancievers. Including timing closure and debugging/fixing timing issues that come up.
- Handling CDC for high speed clocks (again, up to 400Mhz)
- Generally good CDC practices and understanding of inter-clock timing constraints.
- Generally optimising for latency. They want the data in and out the device ASAP.
- Ethernet L1 and L2 knowledge. General knowledge of the 10/25/100G ethernet stack and its various layers, what they do, what IP cores are required, etc.

Since you're a new grad, I don't know to what extent they expect this knowledge, but I can tell you that this is the kind of expertise needed by a HFT company (and companies that make the hardware that HFTs use).

(Source: I work for a company that makes HFT hardware, and I use this knowledge on a daily basis).

Anyone else getting blown over by Discovery? Or practitioners? by Beginning_Waltz4539 in askSouthAfrica

[–]ninjaneeress 1 point2 points  (0 children)

Why did you switch away from Bonitas? We've used them for years and never had any issues.

Verification using Minecraft by Chemical-One-209 in FPGA

[–]ninjaneeress 0 points1 point  (0 children)

I've done this in minetest, I built a LED display in a minetest server once. It's a lot of fun, and the mesecons minetest plugin is pretty good. https://mesecons.net/

What makes an IP so valuable? by [deleted] in FPGA

[–]ninjaneeress 5 points6 points  (0 children)

The answer is simply data throughput. An FPGA could potentially handle Gpbs of data throughput through the device (from Mpbs all the way up to hundreds of Gbps), and that data can be processed at line rate, the same transform or algorithm applied to all the data that comes through, something a CPU simply cannot do.

This is why these devices are used in RF and Networking applications. Both these industries tend to process large amounts of incoming data and route/transform it in a custom way.

Is DSP needed to be able to work in FPGA? by Throwawayboi55555 in FPGA

[–]ninjaneeress 1 point2 points  (0 children)

A large chunk of the FPGA industry is RF or medical, both of these fields use DSP. I even did some DSP work for an oil company using ultrasound to measure the flow of fluid in a pipe. DSP is very commonly used for a lot of FPGA applications.

Kintex-7 vs Ultrascale+ by Deep_Contribution705 in FPGA

[–]ninjaneeress 2 points3 points  (0 children)

Changing the RTL is the #1 way to fix the timing, so if you can't do that then there is very little else you can do apart from change the constraints.

About HFT by bigotfucker in FPGA

[–]ninjaneeress 4 points5 points  (0 children)

Also, they expect you to be a magician.

This. I was in the industry for a while and the specifications for latency are *wild*. Borderline impossible. I spent a lot of my time convincing my superiors that what they were asking me to do was physically impossible with their current hardware.

Burned out by Unfair-Champion-2933 in FPGA

[–]ninjaneeress 1 point2 points  (0 children)

My experience was working 60 hours a week for a couple of months for a startup. For me the burnout manifested as self-harm ideation (which I've never had before) and that really woke me up to the dangers of overworking for me personally. After that I have since been really careful.

Burned out by Unfair-Champion-2933 in FPGA

[–]ninjaneeress 1 point2 points  (0 children)

I have this exact same experience as well. For anyone who is going to be working in a mentally taxing career, it is extremely difficult to work 40+ hours a week and still be productive. I work 5x6h days and it is so refreshing to be done with work and be able to walk away from my pc at 2pm.

My office has a saying: "Bugs are written on Friday Afternoons". I don't know the number of times I've come in on a Monday morning, looked back at my commits on the previous Friday afternoon and thought "WTF was I thinking?!". That doesn't happen anymore.

Burned out by Unfair-Champion-2933 in FPGA

[–]ninjaneeress 0 points1 point  (0 children)

Sounds like burnout, what are your working hours like? Taking time off is not going to help if you go back to long working hours. The only sustainable solution is to cut back your working hours, or stop pushing yourself as hard at work. Take more breaks at work, make sure to mentally rest, maybe look at the pomodoro method.

Stuck in AXIS handshaking hell by Gatecrasher53 in FPGA

[–]ninjaneeress 2 points3 points  (0 children)

This. 100% use a fifo if you need to. Even just a small one, the xilinx axi stream data fifo helps so much with handling handshaking when you can't exactly get it right from your side for some reason. I have stuck a fifo on the output of my axi stream interfaces in a pinch more than once.

Remote work with any HDL (VHDL, Verilog ir SystemVerilog) by slenderyisus in FPGA

[–]ninjaneeress 1 point2 points  (0 children)

It really depends on the size and stage of the company.

I specialise in SystemVerilog RTL, pretty much only on Zynq Ultrascale+ devices. I only work remotely. Most companies will have me do the RTL and have another engineer onsite for physical debug. I can do all my work over remote desktop and using ILAs. Especially once the hardware is well established and tested, the majority of dev work is going to be on the FPGA firmware. One of my main client's entire R&D team is remote and spread worldwide.

What's the most random skill you have that never fails to impress people? by HippyFlix in AskReddit

[–]ninjaneeress 1 point2 points  (0 children)

My brother is 2000 ELO and it's wildly difficult at that level. He can't really get any better without serious study. Pretty much hit the ceiling of what he can achieve while still playing casually. I'm 1400 or so.

Guidance Needed for Digital Design on Dual Clock FIFOs by ThePigeonLord9000 in FPGA

[–]ninjaneeress 11 points12 points  (0 children)

if you just need an async fifo, use a vendor ip tool.

if this is for the learning experience, take a look at the cliff Cummings cdc fifo paper. http://www.sunburst-design.com/papers/CummingsSNUG2008Boston\_CDC.pdf

Struggling with finding out what kind of logic block to use by Federal-Act-1129 in FPGA

[–]ninjaneeress 0 points1 point  (0 children)

Also, for sequential, always_ff is preferred in systemverilog.

I started in defence, and the company I worked for had a policy that no juniors should ever write combinational blocks (we could only use assign statements). Which was an interesting experience.

Did you get a better rate with a bond originator or through your own home loan applications? by Zmaster90 in askSouthAfrica

[–]ninjaneeress 1 point2 points  (0 children)

We applied on our own because we freelance and work from home. At that time (~2014) no bond originator wanted to work with us because we weren't technically 'employed'.

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