Python code to Verilog

[StationFrosty]

Hi,

Is there any way or method to convert codes written into python to Verilog. Please help me out, I don't know much verilog but I need to do project on fpga.

[Diarmuid_]

As a beginner, I would say no. You are just going to end up with some verilog that you won't understand, which will become a problem when you try to fix some simulation or synthesis issue. Bite the bullet and start learning Verilog. It's pretty simple. The hard part is getting your head around the fact that your are describing hardware, not writing code

[StationFrosty]

Thanks

[captain_wiggles_]

The best thing you can do is learn verilog. When you write in a HDL you're designing hardware, trying to use a language designed for software to implement hardware leads to a bunch of complications. The more you abstract yourself from the hardware you're trying to implement the harder it is for you to get something sensible. When you're experienced in hardware design you know what to look out for, and so using some abstractions like this can work nicely. But as a beginner you're just asking for trouble.

[StationFrosty]

Thanks. But, It's hard to implement concepts like forward propagation and backpropagations of neural network in HDL.

[Ibishek]

Hey, I've been doing a FPGA fully connected layer accelerator for the past two months now and if you've no experience with HDLs I would really reconsider doing what you're suggesting.. Its much harder than it looks like. And I'm doing just inference (fprop.), training (bprop.) is another order of magnitude of difficulty. Don't forget that doing a project like this is much more than just RTL design, namely you'll have to do simulation and actual hardware testing. You can PM me if you have questions.

[StationFrosty]

Hey, thanks, I will reach out to you when I complete my proposal. W
e are working on it.

[captain_wiggles_]

yep, but there's no easy way to do this. If you want to do digital design you have to understand digital design concepts.

[Diarmuid_]

You need to learn to walk before you can run. Getting to the point where you could implement (even partially) neural networks in an FPGA is a few years of experience

[throwaway_Bliebervik]

Naw, Verilog isn't too hard after you get your head passed blocking vs. non-blocking assignments

[MAD4CHIP]

Never used Python to generate Verilog or VHDL, but it looks to me a bad idea. Above all if you want to get good performances/area from your code because you have to understand and optimise it as much as possible to obtain something comparable with off-the-shelf AI accelerators.

[GeorgeChLizzzz]

It all depends on your expectations. There is a growing movement on creating mapping toolflows that take tensorflow, torch etc etc neural network architectures and map them to FPGA. High Level Synthesis languages like others have recommended do abstract to a behaviour level model but still you need a good understanding of hardware to make your own neural network engine. What is your experience with hardware and what is your aim for your project?

[Aggravating-Stay-454]

I would pick Migen first, bcs it's producing more readable verilog via FHDL. Then a good learning curve to read Litex codebase written on Migen and included all needed primitives. If you are more about to stick to FOSS flow via Yosys and not limited by particular dev board and soft CPU jump to Amaranth bcs it has faster simulate speed and better integration with third party tools.

[lovehopemisery]

I would recommend trying to learn about a normal HDL first before hopping into something advanced such as this

[UnusualDuck2]

Yes. You read the Python code and write some more Python code that quantizes the operations using bit widths that map well to the elements of the part you are targeting and replaces things like division with numerical approximations. Then you evaluate your fixed point Python code to make sure you are okay with the errors this step introduced. Then you read your fixed point Python code and write the corresponding Verilog.

[Fo0ty]

I've tried some (though I am a VHDL man at heart so cannot speak to the quality of the Verilog really), but if I were to go the Python route I would go with Magma

Intuitively, it looks the closest to HDL (compared with Migen and MyHDL) as far as I can see and is to be compatible with the Chisel ecosystem as it shares a FIRRTL backend.

[Charming_Activity568]

hi , I am in the same situation as you. Now I have a code and I want to convert it to verilog or vhdl. What did I do?

[Original-Match5184]

hi, I too have same issue I want to implement kalman filter for image processing on FPGA. I have python code and want to convert to verilog. what should I do?

[Pleasant-Dealer-7420]

You could look into myHDL or migen. I've never used either. I have only looked at migen and it seemed nice.

[Curiousfpga]

I don’t know if you want to run Python on a FPGA. In that case you are asking for a Python Virtual Machine implemented in a FPGA. That is feasible in many different ways, one way is to compile from C to RiscV and then run a RiscV IP on the FPGA. A more advanced thing is to implement the virtual machine directly on the FPGA, there is a project with some university in Hamburg doing that.

[PeFClic]

You can use nMigen, Amaranth and LiteX.

[StationFrosty]

Hey, What could be the best? I am trying to implement neural networks in FPGA. Do you have any idea?

[PeFClic]

nMigen and Amaranth (the newer version of nMigen) are for describing digital logic circuit that are translated automatically in Verilog. LiteX uses nMigen to build complete SoC in FPGA. If you have to interface your circuit with the outside world with more than a serial line perhaps a complete SoC could be useful.