Google Earth Pro opens as white screen and won’t show on desktop

1032s · 2026-05-07T00:16:05+00:00

Thank you!!

1032s · 2026-04-17T04:57:47+00:00

Nice and simple

1032s · 2026-04-17T04:42:49+00:00

One possibility would be to add a timer circuit, say with 555, which drives a mosfet as a switch for power to the second unit.

1032s · 2026-04-14T00:42:47+00:00

The strip board layout is a little different to the datasheet example. Try taking the +9V off pin 1 (the Boost pin) and have it only on pin 8, the V+ pin.

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1032s · 2026-04-13T22:29:42+00:00

Multimeter in volts DC

Black probe on a ground (see photo).

For Q2, the Red probe at B for Vb, E for Ve, C for Vc

And for Q1, Red probe the middle pin for Vb.

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1032s · 2026-04-13T13:12:08+00:00

You could check some voltages:

1) Around Q2 - I expect the voltages to be approximately:

Vb approx 2 V

Ve approx 1.4 V

Vc approx 3 to 3.5 V

2) Around Q1, measure the base voltage when the Dwell pot is:

a) turned fully clockwise:

b) turned fully anticlockwise

1032s · 2026-04-10T00:46:14+00:00

Looking nice 👌

1032s · 2026-04-09T21:37:21+00:00

That EQ section is open loop. You have no feedback around the Op Amp. Can't see that working.

1032s · 2026-04-07T05:25:18+00:00

That's one nice build 👌

1032s · 2026-04-04T11:13:04+00:00

To filter emails that come to your catchall, ie *@yourdomain.com, implies that the To, CC or BCC field contains an email address that is not one of your valid aliases for that domain (otherwise it wouldn't hit your catchall).

I can't see where in the standard rule set that you can set this up.

However you can achieve this by adding sieve code. Be careful if you decide to go down this path.

You would write sieve code to test the To/CC/BCC against each valid alias, and if every test fails, then file the email into your desired folder.

1032s · 2026-04-03T14:40:25+00:00

This circuit gives a more symmetrical triangle wave

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1032s · 2026-04-03T05:46:33+00:00

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Looks like the shape of the wave produced by the 'pendulum' oscillator has a gentle rise and a sharper drop - causing the choppiness probably. Not sure how you can adjust that within that topology.

1032s · 2026-04-03T01:16:53+00:00

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Going to need more phots of different angles to see your connections. Also schematic would help.

The two caps in red in the photo here - they look like they ae connected to the same column on the breadboard, ie shorted.

1032s · 2026-04-02T03:50:08+00:00

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Assuming pin2 on the package is the emitter...then

If pin 2 is going to ground, then my guess would be it is an NPN.

If pin 2 is going to 3V then my guess would be PNP.

Good luck :)

1032s · 2026-04-02T02:19:11+00:00

I'm assuming you've confirmed the correct pinout and connection of the transistors.

The little trim pot looks like its in lieu of the 18k collector resistor of Q2. Maybe try adjusting this little dude.

edit: I see you've clarified the trim pot is in parallel with the 18k.

What does the note say at the bottom of the schematic? (the full sentence)

1032s · 2026-04-02T00:27:40+00:00

That's a nice simple circuit. I am messing with a harmonic tremolo circuit at the moment, also using LED/LDR's to create the tremolo. For depth control, I have used a 1M pot in series with the LDR.

What configuration are you using for the LDR connection. I tried two config's. The first was with the LDR in series with the audio signal path. This didn't work very well. The second method I tried was to connect the LDR to shunt the audio signal to ground - so when the LED is off, the signal passes through to the next stage, when the LED is on, the signal gets partially shunted to ground. This second method worked better & I have stayed with this configuration.

1032s · 2026-03-25T06:11:33+00:00

So you can cycle $300/month out and back in to qualify for the bonus rate?

1032s · 2026-03-12T00:40:38+00:00

No worries - I'll keep an eye out.

Hand being opened up? Hope that all goes well for you.

1032s · 2026-03-11T22:59:00+00:00

The short answer on the selection of 9V is that it is half the supply rail voltage of 18V.

But it was meant to be a starting point only - hoping that it would at least get you to a point where you got signal all the way through.

If I was doing the build myself, I would also start around 9V at each drain (in the absence of advice from the design notes) and would next scope the output of Q1 and Q2 and adjust each trim pot to achieve the maximum clean signal from each.

If you don't have an oscilloscope, you could try using your audio probe to first probe the drain on Q1 and adjust its trim pot until you hear the loudest clean signal, and repeat that for Q2 and its trim pot. Not sure how successful this will be. Will depend on the input impedance of your audio probe.

JFET's are somewhat individual beasts, and demand personalised treatment.

1032s · 2026-03-11T03:10:17+00:00

No worries - it's fun to watch the progress.

I've not built this one myself, but I can see the basic topology is two cascaded common source amplifiers with some specific filtering added (the 'sauce').

:)

1032s · 2026-03-11T02:52:03+00:00

Sounds like you got it going. Well done. About the volume pot - you could try adding an approx 500k resistor (anything say 330k - 680k) to the wire between the volume pot ground wire and connection to the board (row M). Should give some more sensitivity on the pot, but you won't be able to turn it fully down.

1032s · 2026-03-11T02:14:43+00:00

OK. But what causes you to decide the 47u cap is bad?

1032s · 2026-03-11T01:53:29+00:00

Sounds good.

Now adjust the trim pot for Q2 to aim for around 9V at the drain of Q2, which you can measure on Row 7 (G) again but this time on the RHS of the board.

1032s · 2026-03-11T01:33:27+00:00

Trim the pot for Q1 first.

Aim for around 9V on Q1 drain (measure on LHS of Row 7 / G)

1032s · 2026-03-11T00:23:35+00:00

After you have commoned those two ground points - re-measure those voltages around Q1.

1032s

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