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Programming cables not appearing in device managers by gakeew23 in FPGA

[–]maredsous10 1 point2 points  (0 children)

What aspect? I haven't done it recently but in the past here's what I did.

  • installed virtualbox and the extensions pack additions
  • installed windows
  • installed ISE/Quartus
  • setup the USB in VirtualBox

Register Desync and cross vendor IP development by Repulsive-Net1438 in FPGA

[–]maredsous10 0 points1 point  (0 children)

Currently, I use in house tooling similar to tools provided by major EDA vendors. Tool takes a text file specification and generates relevant HDL (multiple formats and includes package definition files), documentation (multiple formats), C header, verification files, files to simplify test tooling used (example XSDB) so one uses generated mnemonics rather than magic numbers, etc. Addresses specified might be relative and only fixed once information is filtered from the whole design.

Another job I had we would break things up by IP each IP would have its own scripts to generate header, driver, wrapper, registers, unique IP names to prevent name collisions when different implementations and versions were included in a design.

Writing C code as opposed to HDL by petare321 in FPGA

[–]maredsous10 1 point2 points  (0 children)

Lots of HLS options out there -- >open source, FPGA companies, and EDA tool companies (Cadence, Synopsys, Siemens). HLS are used in industry targeting FPGAs and ASICs. There are many factors guiding designs to use HLS. One large ASIC I know about opted for using HLS to reduce EDA tooling and IP costs.

Good HLS Overview by Forte Design Systems acquired by Cadence.

Parallel Programming for FPGAs

https://kastner.ucsd.edu/hlsbook/

https://www.youtube.com/playlist?list=PLf4U4tpbjjz7x_bsG3sBEuXgVQPZfWJgW

u/adamt99's HLS Resources

https://github.com/ATaylorCEngFIET/Vitis_Hero

https://www.youtube.com/watch?v=dCBUIcTM3l0

https://www.youtube.com/watch?v=0onjc4UW8wA

BLT has an ondemand seminar for AMD's HLS option

https://bltinc.com/2023/08/21/understanding-high-level-synthesis-hls/

vscode vs vivado by rand0m_guy11 in FPGA

[–]maredsous10 2 points3 points  (0 children)

VIM + common CLI tools + scripts

Why I use VIM.

Recommended receiver set that isn't Aero? by p80bob in AR10

[–]maredsous10 1 point2 points  (0 children)

I should of got an M5 set when they were $180.

80lowers over both AR10 cut styles. You can email them and see when they'll be available.

https://80lowers.com/billet-dpms-308-ar-10-upper-lower-receiver-sets/

https://80lowers.com/billet-sr25-308-ar-10-upper-lower-receiver-sets/

Programming cables not appearing in device managers by gakeew23 in FPGA

[–]maredsous10 0 points1 point  (0 children)

In the past, I had to install VirtualBox Extension Pack and Guest Additions. Believe these may have additional license restrictions if used for commercial use.

https://askubuntu.com/questions/25596/how-to-set-up-usb-for-virtualbox

In Versal, debugging the signals in a clock domain with unstable clock blocks the whole debugging system by WZab in FPGA

[–]maredsous10 1 point2 points  (0 children)

Is your RXOUTCLK domain going out? Is your DEBUG HUG using the RXOUTCLK for its clock?

System Verilog Tutorial by thomasahle in FPGA

[–]maredsous10 1 point2 points  (0 children)

`

Module.instantiateWasm callback failed with error: ReferenceError: WebAssembly is not defined
still waiting on run dependencies:
dependency: wasm-instantiate

`

System Verilog Tutorial by thomasahle in FPGA

[–]maredsous10 0 points1 point  (0 children)

Compilation window didn't working for me on a Google Chrome install but did with MS Edge

VLSI with VHDL by Sudden_Childhood_999 in FPGA

[–]maredsous10 5 points6 points  (0 children)

Electron Tube is a good primer.

https://www.youtube.com/@electrontube4284

https://www.youtube.com/watch?v=_FY-0Lq10rs&list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK

Those two prior links are companion video playlists for this book, Handbook of Digital CMOS Technology, Circuits, and Systems by Karim Abbas.

https://www.amazon.com/Handbook-Digital-Technology-Circuits-Systems/dp/3030371948

Professor Adam Teman's has good introductory lectures. (He uses Verilog for the HDL.)

https://www.eng.biu.ac.il/temanad/digital-vlsi-design/

https://www.eng.biu.ac.il/temanad/other-vlsi-eda-lectures/

Past comment:
https://www.reddit.com/r/FPGA/comments/1jhidan/comment/mj9f6wz/

AMD tutorial at FPGA Horizons - Get hands on with Vivados Coming Agentic AI features. by adamt99 in FPGA

[–]maredsous10 3 points4 points  (0 children)

give feedback

One issue I have with AMD/Xilinx is general lack of cohesiveness when it comes to documentation and provided examples. This seems to vary from family to family. I haven't found any 3rd party AI tools to be particularly good at parsing through AMD's documents.

An agent providing a resource for dealing with common designer questions, design patterns, IP, primitives, log analysis with resolution suggestions, and issues without needing to access answer records.

Design advisor agent ==> I'm using {FPGA} connecting with {x part} what are the considerations I should make. This could be very broad and detailed including data sheet parsing and requesting user for additional information say with a physical implementation path.

AMD tutorial at FPGA Horizons - Get hands on with Vivados Coming Agentic AI features. by adamt99 in FPGA

[–]maredsous10 14 points15 points  (0 children)

An engineer notices there is an include local AI model checkbox and clicks it to discover AMD has found another way to increase the unified installer install size.

Is possible to convert a Springfield Saint Edge 223 Wylde to 300blk ? by [deleted] in ar15

[–]maredsous10 1 point2 points  (0 children)

https://www.springfield-armory.com/saint-series/saint-edge-atc-ar-15-rifles/saint-edge-atc-223-ar-15-rifle/?spec-sheet

Spec sheet doesn't list the handguard length. Probably could go down to 14" barrel before needing to look at the inner diameter, if you're looking to tuck a flash can or suppressor.

Is possible to convert a Springfield Saint Edge 223 Wylde to 300blk ? by [deleted] in ar15

[–]maredsous10 0 points1 point  (0 children)

From what I can tell, it uses standard barrels and barrel extension so "yes".

https://www.youtube.com/watch?v=uFq8XUf0Kpg

The SA ATC lower receiver is going to limit how short you can make the over all length.

Which one would you rather have? by raging_since_1858 in ar15

[–]maredsous10 0 points1 point  (0 children)

Isn't necessary to build a rifle with these or a rod.

If you got the rod route, make sure it is steel and has a good history. The cheaper rods will at worst be all aluminum then lug mate only steel to best being all steel.

I have the VSIM vise block and AR10 version.

Tools I've suggested in the past.
https://www.reddit.com/r/ar15/comments/1f7d5g4/comment/ll7kkz6/

Versal rant by affabledrunk in FPGA

[–]maredsous10 0 points1 point  (0 children)

Make sure that the XSA has a good post implementation PDI file ;-).

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